upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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308 lines
7.0 KiB
308 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de>
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*
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* This code is mostly based on the code extracted from this MediaTek
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* github repository:
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*
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* https://github.com/MediaTek-Labs/linkit-smart-uboot.git
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*
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* I was not able to find a specific license or other developers
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* copyrights here, so I can't add them here.
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*
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* Most functions in this file are copied from the MediaTek U-Boot
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* repository. Without any documentation, it was impossible to really
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* implement this differently. So its mostly a cleaned-up version of
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* the original code, with only support for the MT7628 / MT7688 SoC.
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <asm/cacheops.h>
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#include <asm/io.h>
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#include "mt76xx.h"
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#define NUM_OF_CACHELINE 128
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#define MIN_START 6
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#define MIN_FINE_START 0xf
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#define MAX_START 7
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#define MAX_FINE_START 0x0
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#define CPU_FRAC_DIV 1
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
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#define DRAM_BUTTOM 0x02000000
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
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#define DRAM_BUTTOM 0x04000000
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
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#define DRAM_BUTTOM 0x08000000
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
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#define DRAM_BUTTOM 0x10000000
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#endif
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static inline void cal_memcpy(void *src, void *dst, u32 size)
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{
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u8 *psrc = (u8 *)src;
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u8 *pdst = (u8 *)dst;
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int i;
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for (i = 0; i < size; i++, psrc++, pdst++)
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*pdst = *psrc;
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}
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static inline void cal_memset(void *src, u8 pat, u32 size)
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{
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u8 *psrc = (u8 *)src;
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int i;
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for (i = 0; i < size; i++, psrc++)
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*psrc = pat;
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}
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#define pref_op(hint, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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"pref %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (hint), "R" (*(u8 *)(addr)))
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static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
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{
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u32 *addr = (u32 *)start_addr;
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int i;
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for (i = 0; i < size; i++)
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addr[i] = start_addr + i + bias;
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}
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static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
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u32 offs, u32 pat, u32 val)
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{
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u32 nc_addr;
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u32 *c_addr;
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int i;
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for (nc_addr = 0xa0000000;
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nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
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nc_addr += (DRAM_BUTTOM >> 6) + offs) {
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writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
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wmb(); /* Make sure store if finished */
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c_addr = (u32 *)(nc_addr & 0xdfffffff);
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cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
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cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
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if (dqs > 0)
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writel(0x00000074 |
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(((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
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(((k == 0) ? val : test_dqs) << 8),
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(void *)MT76XX_MEMCTRL_BASE + 0x64);
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else
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writel(0x00007400 |
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(((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
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(((k == 0) ? val : test_dqs) << 0),
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(void *)MT76XX_MEMCTRL_BASE + 0x64);
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wmb(); /* Make sure store if finished */
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invalidate_dcache_range((u32)c_addr,
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(u32)c_addr +
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NUM_OF_CACHELINE * 32);
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wmb(); /* Make sure store if finished */
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for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
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if (i % 8 == 0)
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pref_op(0, &c_addr[i]);
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}
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for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
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if (c_addr[i] != nc_addr + i + pat)
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return -1;
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}
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}
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return 0;
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}
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void ddr_calibrate(void)
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{
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u32 min_coarse_dqs[2];
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u32 max_coarse_dqs[2];
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u32 min_fine_dqs[2];
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u32 max_fine_dqs[2];
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u32 coarse_dqs[2];
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u32 fine_dqs[2];
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int reg = 0, ddr_cfg2_reg;
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int flag;
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int i, k;
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int dqs = 0;
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u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
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u32 val;
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u32 fdiv = 0, frac = 0;
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/* Setup clock to run at full speed */
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val = readl((void *)MT76XX_DYN_CFG0_REG);
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fdiv = (u32)((val >> 8) & 0x0F);
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if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
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frac = val & 0x0f;
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else
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frac = CPU_FRAC_DIV;
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while (frac < fdiv) {
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val = readl((void *)MT76XX_DYN_CFG0_REG);
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fdiv = (val >> 8) & 0x0f;
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fdiv--;
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val &= ~(0x0f << 8);
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val |= (fdiv << 8);
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writel(val, (void *)MT76XX_DYN_CFG0_REG);
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udelay(500);
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val = readl((void *)MT76XX_DYN_CFG0_REG);
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fdiv = (val >> 8) & 0x0f;
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}
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clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
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ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
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clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
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(0x3 << 28) | (0x3 << 26));
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min_coarse_dqs[0] = MIN_START;
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min_coarse_dqs[1] = MIN_START;
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min_fine_dqs[0] = MIN_FINE_START;
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min_fine_dqs[1] = MIN_FINE_START;
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max_coarse_dqs[0] = MAX_START;
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max_coarse_dqs[1] = MAX_START;
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max_fine_dqs[0] = MAX_FINE_START;
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max_fine_dqs[1] = MAX_FINE_START;
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dqs = 0;
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/* Add by KP, DQS MIN boundary */
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reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
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coarse_dqs_dll = (reg & 0xf00) >> 8;
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fine_dqs_dll = (reg & 0xf0) >> 4;
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if (coarse_dqs_dll <= 8)
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min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
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else
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min_coarse_dqs_bnd = 0;
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if (fine_dqs_dll <= 8)
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min_fine_dqs_bnd = 8 - fine_dqs_dll;
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else
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min_fine_dqs_bnd = 0;
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/* DQS MIN boundary */
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DQS_CAL:
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for (k = 0; k < 2; k++) {
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u32 test_dqs;
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if (k == 0)
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test_dqs = MAX_START;
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else
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test_dqs = MAX_FINE_START;
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do {
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flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
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0x400, 0x3, 0xf);
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if (flag == -1)
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break;
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test_dqs++;
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} while (test_dqs <= 0xf);
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if (k == 0) {
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max_coarse_dqs[dqs] = test_dqs;
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} else {
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test_dqs--;
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if (test_dqs == MAX_FINE_START - 1) {
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max_coarse_dqs[dqs]--;
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max_fine_dqs[dqs] = 0xf;
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} else {
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max_fine_dqs[dqs] = test_dqs;
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}
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}
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}
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for (k = 0; k < 2; k++) {
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u32 test_dqs;
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if (k == 0)
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test_dqs = MIN_START;
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else
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test_dqs = MIN_FINE_START;
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do {
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flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
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0x480, 0x1, 0x0);
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if (k == 0) {
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if (flag == -1 ||
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test_dqs == min_coarse_dqs_bnd)
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break;
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test_dqs--;
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if (test_dqs < min_coarse_dqs_bnd)
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break;
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} else {
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if (flag == -1) {
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test_dqs++;
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break;
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} else if (test_dqs == min_fine_dqs_bnd) {
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break;
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}
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test_dqs--;
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if (test_dqs < min_fine_dqs_bnd)
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break;
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}
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} while (test_dqs >= 0);
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if (k == 0) {
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min_coarse_dqs[dqs] = test_dqs;
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} else {
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if (test_dqs == MIN_FINE_START + 1) {
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min_coarse_dqs[dqs]++;
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min_fine_dqs[dqs] = 0x0;
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} else {
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min_fine_dqs[dqs] = test_dqs;
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}
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}
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}
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if (dqs == 0) {
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dqs = 1;
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goto DQS_CAL;
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}
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for (i = 0; i < 2; i++) {
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u32 temp;
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coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
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temp =
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(((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
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((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
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if (temp >= 0x10) {
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coarse_dqs[i]++;
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fine_dqs[i] = (temp - 0x10) + 0x8;
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} else {
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fine_dqs[i] = temp;
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}
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}
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reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
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(coarse_dqs[0] << 4) | fine_dqs[0];
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clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
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writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
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writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
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setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
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for (i = 0; i < 2; i++)
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debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
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min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
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debug("\nDDR Calibration DQS reg = %08X\n", reg);
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}
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