upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Jimmy Zhang b9dd6215ce ARM: tegra: don't exceed AVP limits when configuring PLLP ... Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		11 years ago
..
cpu	ARM: tegra: don't exceed AVP limits when configuring PLLP	11 years ago
dts	dts: zynq: Add basic fdt support	12 years ago
imx-common	MX6: fix sata compilation for i.MX6	12 years ago
include/asm	ARM: tegra: don't exceed AVP limits when configuring PLLP	11 years ago
lib	arm: use canonical sub mnemonic	12 years ago
config.mk	ARM: merge commonly-defined PLATFORM_RELFLAGS	12 years ago