upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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157 lines
3.4 KiB
157 lines
3.4 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_fdt.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/sleep.h"
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#include "t104xrdb.h"
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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u8 sw;
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#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
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printf("Board: %sD4RDB\n", cpu->name);
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#else
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printf("Board: %sRDB\n", cpu->name);
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#endif
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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sw = CPLD_READ(flash_ctl_status);
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sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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printf("vBank: %d\n", sw);
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return 0;
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}
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int board_early_init_f(void)
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{
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
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printf("SERDES Reference : 0x%X\n", srds_s1);
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/* select SGMII*/
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if (srds_s1 == 0x86)
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CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
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MISC_CTL_SG_SEL);
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/* select SGMII and Aurora*/
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if (srds_s1 == 0x8E)
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CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
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MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
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#if defined(CONFIG_TARGET_T1040D4RDB)
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if (hwconfig("qe-tdm")) {
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CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
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MISC_MUX_QE_TDM);
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printf("QECSR : 0x%02x, mux to qe-tdm\n",
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CPLD_READ(sfp_ctl_status));
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}
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/* Mask all CPLD interrupt sources, except QSGMII interrupts */
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if (CPLD_READ(sw_ver) < 0x03) {
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debug("CPLD SW version 0x%02x doesn't support int_mask\n",
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CPLD_READ(sw_ver));
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} else {
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CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
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~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
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}
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fsl_fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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if (hwconfig("qe-tdm"))
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fdt_del_diu(blob);
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return 0;
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}
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