upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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177 lines
4.2 KiB
177 lines
4.2 KiB
/*
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* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include "caddy.h"
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static struct caddy_interface *caddy_interface;
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void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
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{
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struct caddy_answer *answer;
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uint32_t ptr;
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answer = &caddy_interface->answer[caddy_interface->answer_in];
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memset((void *)answer, 0, sizeof(struct caddy_answer));
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answer->answer = cmd->cmd;
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answer->issue = cmd->issue;
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answer->status = status;
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memcpy(answer->par, result, 5 * sizeof(result[0]));
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ptr = caddy_interface->answer_in + 1;
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ptr = ptr & (ANSWER_SIZE - 1);
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if (ptr != caddy_interface->answer_out)
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caddy_interface->answer_in = ptr;
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}
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int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned long base_addr;
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uint32_t ptr;
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struct caddy_cmd *caddy_cmd;
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uint32_t result[5];
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uint16_t data16;
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uint8_t data8;
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uint32_t status;
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pci_dev_t dev;
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void *pci_ptr;
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if (argc < 2) {
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puts("Missing parameter\n");
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return 1;
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}
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base_addr = simple_strtoul(argv[1], NULL, 16);
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caddy_interface = (struct caddy_interface *) base_addr;
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memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
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memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
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while (ctrlc() == 0) {
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if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
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memset(result, 0, 5 * sizeof(result[0]));
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status = 0;
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caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
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pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
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(caddy_cmd->addr & 0x001fffff);
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switch (caddy_cmd->cmd) {
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case CADDY_CMD_IO_READ_8:
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result[0] = in_8(pci_ptr);
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break;
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case CADDY_CMD_IO_READ_16:
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result[0] = in_be16(pci_ptr);
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break;
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case CADDY_CMD_IO_READ_32:
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result[0] = in_be32(pci_ptr);
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break;
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case CADDY_CMD_IO_WRITE_8:
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data8 = caddy_cmd->par[0] & 0x000000ff;
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out_8(pci_ptr, data8);
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break;
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case CADDY_CMD_IO_WRITE_16:
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data16 = caddy_cmd->par[0] & 0x0000ffff;
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out_be16(pci_ptr, data16);
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break;
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case CADDY_CMD_IO_WRITE_32:
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out_be32(pci_ptr, caddy_cmd->par[0]);
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break;
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case CADDY_CMD_CONFIG_READ_8:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_byte(dev,
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caddy_cmd->addr,
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&data8);
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result[0] = data8;
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break;
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case CADDY_CMD_CONFIG_READ_16:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_word(dev,
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caddy_cmd->addr,
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&data16);
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result[0] = data16;
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break;
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case CADDY_CMD_CONFIG_READ_32:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_dword(dev,
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caddy_cmd->addr,
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&result[0]);
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break;
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case CADDY_CMD_CONFIG_WRITE_8:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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data8 = caddy_cmd->par[3] & 0x000000ff;
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status = pci_write_config_byte(dev,
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caddy_cmd->addr,
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data8);
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break;
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case CADDY_CMD_CONFIG_WRITE_16:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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data16 = caddy_cmd->par[3] & 0x0000ffff;
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status = pci_write_config_word(dev,
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caddy_cmd->addr,
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data16);
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break;
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case CADDY_CMD_CONFIG_WRITE_32:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_write_config_dword(dev,
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caddy_cmd->addr,
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caddy_cmd->par[3]);
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break;
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default:
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status = 0xffffffff;
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break;
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}
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generate_answer(caddy_cmd, status, &result[0]);
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ptr = caddy_interface->cmd_out + 1;
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ptr = ptr & (CMD_SIZE - 1);
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caddy_interface->cmd_out = ptr;
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}
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caddy_interface->heartbeat++;
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}
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return 0;
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}
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U_BOOT_CMD(
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caddy, 2, 0, do_caddy,
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"Start Caddy server.",
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"Start Caddy server with Data structure a given addr\n"
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);
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