upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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1001 lines
25 KiB
1001 lines
25 KiB
/*
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* (C) Copyright 2001
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* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*************************************************************************
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* changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
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*
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************************************************************************/
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/*
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* mpsc.c - driver for console over the MPSC.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/cache.h>
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#include <malloc.h>
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#include "mpsc.h"
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#include "mv_regs.h"
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#include "../include/memory.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Define this if you wish to use the MPSC as a register based UART.
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* This will force the serial port to not use the SDMA engine at all.
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*/
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#undef CONFIG_MPSC_DEBUG_PORT
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int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
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char (*mpsc_getchar) (void) = mpsc_getchar_debug;
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int (*mpsc_test_char) (void) = mpsc_test_char_debug;
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static volatile unsigned int *rx_desc_base = NULL;
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static unsigned int rx_desc_index = 0;
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static volatile unsigned int *tx_desc_base = NULL;
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static unsigned int tx_desc_index = 0;
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/* local function declarations */
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static int galmpsc_connect (int channel, int connect);
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static int galmpsc_route_rx_clock (int channel, int brg);
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static int galmpsc_route_tx_clock (int channel, int brg);
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static int galmpsc_write_config_regs (int mpsc, int mode);
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static int galmpsc_config_channel_regs (int mpsc);
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static int galmpsc_set_char_length (int mpsc, int value);
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static int galmpsc_set_stop_bit_length (int mpsc, int value);
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static int galmpsc_set_parity (int mpsc, int value);
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static int galmpsc_enter_hunt (int mpsc);
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static int galmpsc_set_brkcnt (int mpsc, int value);
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static int galmpsc_set_tcschar (int mpsc, int value);
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static int galmpsc_set_snoop (int mpsc, int value);
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static int galmpsc_shutdown (int mpsc);
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static int galsdma_set_RFT (int channel);
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static int galsdma_set_SFM (int channel);
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static int galsdma_set_rxle (int channel);
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static int galsdma_set_txle (int channel);
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static int galsdma_set_burstsize (int channel, unsigned int value);
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static int galsdma_set_RC (int channel, unsigned int value);
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static int galbrg_set_CDV (int channel, int value);
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static int galbrg_enable (int channel);
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static int galbrg_disable (int channel);
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static int galbrg_set_clksrc (int channel, int value);
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static int galbrg_set_CUV (int channel, int value);
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static void galsdma_enable_rx (void);
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static int galsdma_set_mem_space (unsigned int memSpace,
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unsigned int memSpaceTarget,
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unsigned int memSpaceAttr,
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unsigned int baseAddress,
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unsigned int size);
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#define SOFTWARE_CACHE_MANAGEMENT
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#ifdef SOFTWARE_CACHE_MANAGEMENT
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#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
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#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
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#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
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#else
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#define FLUSH_DCACHE(a,b)
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#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
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#define INVALIDATE_DCACHE(a,b)
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#endif
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#ifdef CONFIG_MPSC_DEBUG_PORT
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static void mpsc_debug_init (void)
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{
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volatile unsigned int temp;
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/* Clear the CFR (CHR4) */
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/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
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temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
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temp &= 0xffffff00;
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temp |= BIT29;
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GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
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temp);
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/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
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temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
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temp |= (BIT12 | BIT15);
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GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
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temp);
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/* Set int mask */
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temp = GTREGREAD (GALMPSC_0_INT_MASK);
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temp |= BIT6;
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GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
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}
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#endif
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char mpsc_getchar_debug (void)
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{
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volatile int temp;
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volatile unsigned int cause;
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cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
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while ((cause & BIT6) == 0) {
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cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
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}
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temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
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(CHANNEL * GALMPSC_REG_GAP));
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/* By writing 1's to the set bits, the register is cleared */
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GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
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temp);
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GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
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return (temp >> 16) & 0xff;
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}
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/* special function for running out of flash. doesn't modify any
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* global variables [josh] */
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int mpsc_putchar_early (char ch)
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{
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int mpsc = CHANNEL;
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int temp =
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GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
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galmpsc_set_tcschar (mpsc, ch);
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GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
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temp | 0x200);
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#define MAGIC_FACTOR (10*1000000)
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udelay (MAGIC_FACTOR / gd->baudrate);
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return 0;
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}
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/* This is used after relocation, see serial.c and mpsc_init2 */
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static int mpsc_putchar_sdma (char ch)
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{
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volatile unsigned int *p;
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unsigned int temp;
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/* align the descriptor */
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p = tx_desc_base;
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memset ((void *) p, 0, 8 * sizeof (unsigned int));
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/* fill one 64 bit buffer */
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/* word swap, pad with 0 */
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p[4] = 0; /* x */
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p[5] = (unsigned int) ch; /* x */
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/* CHANGED completely according to GT64260A dox - NTL */
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p[0] = 0x00010001; /* 0 */
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p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
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p[2] = 0; /* 8 */
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p[3] = (unsigned int) &p[4]; /* c */
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#if 0
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p[9] = DESC_FIRST | DESC_LAST;
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p[10] = (unsigned int) &p[0];
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p[11] = (unsigned int) &p[12];
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#endif
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FLUSH_DCACHE (&p[0], &p[8]);
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GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
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(unsigned int) &p[0]);
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GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
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(unsigned int) &p[0]);
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temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
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temp |= (TX_DEMAND | TX_STOP);
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GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
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INVALIDATE_DCACHE (&p[1], &p[2]);
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while (p[1] & DESC_OWNER_BIT) {
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udelay (100);
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INVALIDATE_DCACHE (&p[1], &p[2]);
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}
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return 0;
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}
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char mpsc_getchar_sdma (void)
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{
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static unsigned int done = 0;
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volatile char ch;
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unsigned int len = 0, idx = 0, temp;
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volatile unsigned int *p;
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do {
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p = &rx_desc_base[rx_desc_index * 8];
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INVALIDATE_DCACHE (&p[0], &p[1]);
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/* Wait for character */
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while (p[1] & DESC_OWNER_BIT) {
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udelay (100);
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INVALIDATE_DCACHE (&p[0], &p[1]);
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}
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/* Handle error case */
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if (p[1] & (1 << 15)) {
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printf ("oops, error: %08x\n", p[1]);
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temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
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(CHANNEL * GALMPSC_REG_GAP));
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temp |= (1 << 23);
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GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
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(CHANNEL * GALMPSC_REG_GAP), temp);
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/* Can't poll on abort bit, so we just wait. */
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udelay (100);
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galsdma_enable_rx ();
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}
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/* Number of bytes left in this descriptor */
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len = p[0] & 0xffff;
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if (len) {
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/* Where to look */
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idx = 5;
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if (done > 3)
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idx = 4;
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if (done > 7)
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idx = 7;
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if (done > 11)
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idx = 6;
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INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
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ch = p[idx] & 0xff;
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done++;
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}
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if (done < len) {
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/* this descriptor has more bytes still
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* shift down the char we just read, and leave the
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* buffer in place for the next time around
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*/
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p[idx] = p[idx] >> 8;
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FLUSH_DCACHE (&p[idx], &p[idx + 1]);
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}
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if (done == len) {
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/* nothing left in this descriptor.
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* go to next one
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*/
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p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
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p[0] = 0x00100000;
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FLUSH_DCACHE (&p[0], &p[1]);
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/* Next descriptor */
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rx_desc_index = (rx_desc_index + 1) % RX_DESC;
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done = 0;
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}
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} while (len == 0); /* galileo bug.. len might be zero */
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return ch;
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}
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int mpsc_test_char_debug (void)
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{
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if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
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return 0;
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else {
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return 1;
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}
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}
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int mpsc_test_char_sdma (void)
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{
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volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
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INVALIDATE_DCACHE (&p[1], &p[2]);
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if (p[1] & DESC_OWNER_BIT)
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return 0;
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else
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return 1;
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}
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int mpsc_init (int baud)
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{
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/* BRG CONFIG */
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galbrg_set_baudrate (CHANNEL, baud);
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galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
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galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
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galbrg_enable (CHANNEL); /* Enable BRG */
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/* Set up clock routing */
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galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
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galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
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galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
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/* reset MPSC state */
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galmpsc_shutdown (CHANNEL);
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/* SDMA CONFIG */
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galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
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galsdma_set_txle (CHANNEL);
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galsdma_set_rxle (CHANNEL);
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galsdma_set_RC (CHANNEL, 0xf);
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galsdma_set_SFM (CHANNEL);
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galsdma_set_RFT (CHANNEL);
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/* MPSC CONFIG */
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galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
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galmpsc_config_channel_regs (CHANNEL);
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galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
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galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
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galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
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#ifdef CONFIG_MPSC_DEBUG_PORT
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mpsc_debug_init ();
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#endif
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/* COMM_MPSC CONFIG */
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#ifdef SOFTWARE_CACHE_MANAGEMENT
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galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
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#else
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galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
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#endif
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return 0;
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}
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void mpsc_sdma_init (void)
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{
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/* Setup SDMA channel0 SDMA_CONFIG_REG*/
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GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
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/* Enable MPSC-Window0 for DRAM Bank0 */
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if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
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MV64460_SDMA_DRAM_CS_0_TARGET,
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0,
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memoryGetBankBaseAddress
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(CS_0_LOW_DECODE_ADDRESS),
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memoryGetBankSize (BANK0)) != true)
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printf ("%s: SDMA_Window0 memory setup failed !!! \n",
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__FUNCTION__);
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/* Disable MPSC-Window1 */
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if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
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MV64460_SDMA_DRAM_CS_0_TARGET,
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0,
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memoryGetBankBaseAddress
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(CS_1_LOW_DECODE_ADDRESS),
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memoryGetBankSize (BANK3)) != true)
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printf ("%s: SDMA_Window1 memory setup failed !!! \n",
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__FUNCTION__);
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/* Disable MPSC-Window2 */
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if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
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MV64460_SDMA_DRAM_CS_0_TARGET,
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0,
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memoryGetBankBaseAddress
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(CS_2_LOW_DECODE_ADDRESS),
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memoryGetBankSize (BANK3)) != true)
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printf ("%s: SDMA_Window2 memory setup failed !!! \n",
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__FUNCTION__);
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/* Disable MPSC-Window3 */
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if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
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MV64460_SDMA_DRAM_CS_0_TARGET,
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0,
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memoryGetBankBaseAddress
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(CS_3_LOW_DECODE_ADDRESS),
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memoryGetBankSize (BANK3)) != true)
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printf ("%s: SDMA_Window3 memory setup failed !!! \n",
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__FUNCTION__);
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/* Setup MPSC0 access mode Window0 full access */
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GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
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(MV64460_SDMA_WIN_ACCESS_FULL <<
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(MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
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/* Setup MPSC1 access mode Window1 full access */
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GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
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(MV64460_SDMA_WIN_ACCESS_FULL <<
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(MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
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/* Setup MPSC internal address space base address */
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GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
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/* no high address remap*/
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GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
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GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
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/* clear interrupt cause register for MPSC (fault register)*/
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GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
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}
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void mpsc_init2 (void)
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{
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int i;
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#ifndef CONFIG_MPSC_DEBUG_PORT
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mpsc_putchar = mpsc_putchar_sdma;
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mpsc_getchar = mpsc_getchar_sdma;
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mpsc_test_char = mpsc_test_char_sdma;
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#endif
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/* RX descriptors */
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rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
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sizeof (unsigned int));
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/* align descriptors */
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rx_desc_base = (unsigned int *)
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(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
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rx_desc_index = 0;
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memset ((void *) rx_desc_base, 0,
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(RX_DESC * 8) * sizeof (unsigned int));
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for (i = 0; i < RX_DESC; i++) {
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rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
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rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
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rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
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rx_desc_base[i * 8] = 0x00100000;
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}
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rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
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FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
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GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
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(unsigned int) &rx_desc_base[0]);
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/* TX descriptors */
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tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
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sizeof (unsigned int));
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/* align descriptors */
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tx_desc_base = (unsigned int *)
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(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
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tx_desc_index = -1;
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memset ((void *) tx_desc_base, 0,
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(TX_DESC * 8) * sizeof (unsigned int));
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for (i = 0; i < TX_DESC; i++) {
|
|
tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
|
|
tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
|
|
tx_desc_base[i * 8 + 3] =
|
|
(unsigned int) &tx_desc_base[i * 8 + 4];
|
|
tx_desc_base[i * 8 + 2] =
|
|
(unsigned int) &tx_desc_base[(i + 1) * 8];
|
|
tx_desc_base[i * 8 + 1] =
|
|
DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
|
|
|
|
/* set sbytecnt and shadow byte cnt to 1 */
|
|
tx_desc_base[i * 8] = 0x00010001;
|
|
}
|
|
tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
|
|
|
|
FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
|
|
|
|
udelay (100);
|
|
|
|
galsdma_enable_rx ();
|
|
|
|
return;
|
|
}
|
|
|
|
int galbrg_set_baudrate (int channel, int rate)
|
|
{
|
|
int clock;
|
|
|
|
galbrg_disable (channel); /*ok */
|
|
|
|
#ifdef ZUMA_NTL
|
|
/* from tclk */
|
|
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
|
|
#else
|
|
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
|
|
#endif
|
|
|
|
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
|
|
|
|
galbrg_enable (channel);
|
|
|
|
gd->baudrate = rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
/* Below are all the private functions that no one else needs */
|
|
|
|
static int galbrg_set_CDV (int channel, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
|
|
temp &= 0xFFFF0000;
|
|
temp |= (value & 0x0000FFFF);
|
|
GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galbrg_enable (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
|
|
temp |= 0x00010000;
|
|
GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galbrg_disable (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
|
|
temp &= 0xFFFEFFFF;
|
|
GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galbrg_set_clksrc (int channel, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
|
|
temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
|
|
temp |= (value << 18);
|
|
GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
|
|
return 0;
|
|
}
|
|
|
|
static int galbrg_set_CUV (int channel, int value)
|
|
{
|
|
/* set CountUpValue */
|
|
GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if 0
|
|
static int galbrg_reset (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
|
|
temp |= 0x20000;
|
|
GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int galsdma_set_RFT (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp |= 0x00000001;
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
|
|
temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galsdma_set_SFM (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp |= 0x00000002;
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
|
|
temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galsdma_set_rxle (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp |= 0x00000040;
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
|
|
temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galsdma_set_txle (int channel)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp |= 0x00000080;
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
|
|
temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galsdma_set_RC (int channel, unsigned int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp &= ~0x0000003c;
|
|
temp |= (value << 2);
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
|
|
temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galsdma_set_burstsize (int channel, unsigned int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
|
|
temp &= 0xFFFFCFFF;
|
|
switch (value) {
|
|
case 8:
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG +
|
|
(channel * GALSDMA_REG_DIFF),
|
|
(temp | (0x3 << 12)));
|
|
break;
|
|
|
|
case 4:
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG +
|
|
(channel * GALSDMA_REG_DIFF),
|
|
(temp | (0x2 << 12)));
|
|
break;
|
|
|
|
case 2:
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG +
|
|
(channel * GALSDMA_REG_DIFF),
|
|
(temp | (0x1 << 12)));
|
|
break;
|
|
|
|
case 1:
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG +
|
|
(channel * GALSDMA_REG_DIFF),
|
|
(temp | (0x0 << 12)));
|
|
break;
|
|
|
|
default:
|
|
return -1;
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_connect (int channel, int connect)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
|
|
|
|
if ((channel == 0) && connect)
|
|
temp &= ~0x00000007;
|
|
else if ((channel == 1) && connect)
|
|
temp &= ~(0x00000007 << 6);
|
|
else if ((channel == 0) && !connect)
|
|
temp |= 0x00000007;
|
|
else
|
|
temp |= (0x00000007 << 6);
|
|
|
|
/* Just in case... */
|
|
temp &= 0x3fffffff;
|
|
|
|
GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_route_rx_clock (int channel, int brg)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_RxC_ROUTE);
|
|
|
|
if (channel == 0) {
|
|
temp &= ~0x0000000F;
|
|
temp |= brg;
|
|
} else {
|
|
temp &= ~0x00000F00;
|
|
temp |= (brg << 8);
|
|
}
|
|
|
|
GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_route_tx_clock (int channel, int brg)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_TxC_ROUTE);
|
|
|
|
if (channel == 0) {
|
|
temp &= ~0x0000000F;
|
|
temp |= brg;
|
|
} else {
|
|
temp &= ~0x00000F00;
|
|
temp |= (brg << 8);
|
|
}
|
|
|
|
GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_write_config_regs (int mpsc, int mode)
|
|
{
|
|
if (mode == GALMPSC_UART) {
|
|
/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
|
|
GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
|
|
0x000004c4);
|
|
|
|
/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
|
|
GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
|
|
0x024003f8);
|
|
/* 22 2222 1111 */
|
|
/* 54 3210 9876 */
|
|
/* 0000 0010 0000 0000 */
|
|
/* 1 */
|
|
/* 098 7654 3210 */
|
|
/* 0000 0011 1111 1000 */
|
|
} else
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_config_channel_regs (int mpsc)
|
|
{
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
|
|
|
|
galmpsc_set_brkcnt (mpsc, 0x3);
|
|
galmpsc_set_tcschar (mpsc, 0xab);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_set_brkcnt (int mpsc, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
|
|
temp &= 0x0000FFFF;
|
|
temp |= (value << 16);
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_set_tcschar (int mpsc, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
|
|
temp &= 0xFFFF0000;
|
|
temp |= value;
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_set_char_length (int mpsc, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
|
|
temp &= 0xFFFFCFFF;
|
|
temp |= (value << 12);
|
|
GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_set_stop_bit_length (int mpsc, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
|
|
temp &= 0xFFFFBFFF;
|
|
temp |= (value << 14);
|
|
GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_set_parity (int mpsc, int value)
|
|
{
|
|
unsigned int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
|
|
if (value != -1) {
|
|
temp &= 0xFFF3FFF3;
|
|
temp |= ((value << 18) | (value << 2));
|
|
temp |= ((value << 17) | (value << 1));
|
|
} else {
|
|
temp &= 0xFFF1FFF1;
|
|
}
|
|
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int galmpsc_enter_hunt (int mpsc)
|
|
{
|
|
int temp;
|
|
|
|
temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
|
|
temp |= 0x80000000;
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
|
|
MPSC_ENTER_HUNT) {
|
|
udelay (1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int galmpsc_shutdown (int mpsc)
|
|
{
|
|
unsigned int temp;
|
|
|
|
/* cause RX abort (clears RX) */
|
|
temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
|
|
temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
|
|
temp &= ~MPSC_ENTER_HUNT;
|
|
GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
|
|
|
|
GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
|
|
GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
|
|
|
|
/* shut down the MPSC */
|
|
GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
|
|
GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
|
|
GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
|
|
|
|
udelay (100);
|
|
|
|
/* shut down the sdma engines. */
|
|
/* reset config to default */
|
|
GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
|
|
|
|
udelay (100);
|
|
|
|
/* clear the SDMA current and first TX and RX pointers */
|
|
GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
|
|
GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
|
|
GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
|
|
|
|
udelay (100);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void galsdma_enable_rx (void)
|
|
{
|
|
int temp;
|
|
|
|
/* Enable RX processing */
|
|
temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
|
|
temp |= RX_ENABLE;
|
|
GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
|
|
|
|
galmpsc_enter_hunt (CHANNEL);
|
|
}
|
|
|
|
static int galmpsc_set_snoop (int mpsc, int value)
|
|
{
|
|
int reg =
|
|
mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
|
|
MPSC_0_ADDRESS_CONTROL_LOW;
|
|
int temp = GTREGREAD (reg);
|
|
|
|
if (value)
|
|
temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
|
|
else
|
|
temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
|
|
GT_REG_WRITE (reg, temp);
|
|
return 0;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
|
|
*
|
|
* DESCRIPTION:
|
|
* the MV64460 SDMA has its own address decoding map that is de-coupled
|
|
* from the CPU interface address decoding windows. The SDMA channels
|
|
* share four address windows. Each region can be individually configured
|
|
* by this function by associating it to a target interface and setting
|
|
* base and size values.
|
|
*
|
|
* NOTE!!!
|
|
* The size must be in 64Kbyte granularity.
|
|
* The base address must be aligned to the size.
|
|
* The size must be a series of 1s followed by a series of zeros
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* true for success, false otherwise.
|
|
*
|
|
*******************************************************************************/
|
|
|
|
static int galsdma_set_mem_space (unsigned int memSpace,
|
|
unsigned int memSpaceTarget,
|
|
unsigned int memSpaceAttr,
|
|
unsigned int baseAddress, unsigned int size)
|
|
{
|
|
unsigned int temp;
|
|
|
|
if (size == 0) {
|
|
GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
|
|
1 << memSpace);
|
|
return true;
|
|
}
|
|
|
|
/* The base address must be aligned to the size. */
|
|
if (baseAddress % size != 0) {
|
|
return false;
|
|
}
|
|
if (size < 0x10000) {
|
|
return false;
|
|
}
|
|
|
|
/* Align size and base to 64K */
|
|
baseAddress &= 0xffff0000;
|
|
size &= 0xffff0000;
|
|
temp = size >> 16;
|
|
|
|
/* Checking that the size is a sequence of '1' followed by a
|
|
sequence of '0' starting from LSB to MSB. */
|
|
while ((temp > 0) && (temp & 0x1)) {
|
|
temp = temp >> 1;
|
|
}
|
|
|
|
if (temp != 0) {
|
|
GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
|
|
(baseAddress | memSpaceTarget | memSpaceAttr));
|
|
GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
|
|
(size - 1) & 0xffff0000);
|
|
GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
|
|
1 << memSpace);
|
|
} else {
|
|
/* An invalid size was specified */
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|