upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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331 lines
12 KiB
331 lines
12 KiB
/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Interphase iSPAN Communications Controllers
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* (453x and others). Tested on 4532.
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*
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* Derived from iSPAN 4539 port (iphase4539) by
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* Wolfgang Grandegger <wg@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
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#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
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/*-----------------------------------------------------------------------
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* If CONFIG_CONS_NONE is defined, then the serial console routines must be
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
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#undef CONFIG_CONS_NONE /* Define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
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/*-----------------------------------------------------------------------
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* Select Ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC).
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*
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* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
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* be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
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#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
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#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
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#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
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#ifdef CONFIG_ETHER_ON_FCC
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#if CONFIG_ETHER_INDEX == 3
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#define CONFIG_SYS_PHY_ADDR 0
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#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
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#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
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#endif /* CONFIG_ETHER_INDEX == 3 */
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#define CONFIG_SYS_CPMFCR_RAMTYPE 0
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#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 3 /* Port D */
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#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
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(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
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#define MDC_DECLARE MDIO_DECLARE
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#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
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#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
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#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
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#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
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#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
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else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
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#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
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else iop->pdat &= ~CONFIG_SYS_MDC_PIN
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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#define CONFIG_8260_CLKIN 65536000 /* in Hz */
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#define CONFIG_BAUDRATE 38400
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_LONGHELP /* #undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
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#define CONFIG_SYS_RESET_ADDRESS 0x09900000
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#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#ifdef CONFIG_BZIP2
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#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#else
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
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/* Environment is in flash, there is little space left in Serial EEPROM */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* If you change bits in the HRCW, you must also change the CONFIG_SYS_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
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*/
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/* 0x1686B245 */
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#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
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HRCW_L2CPC10 | HRCW_ISB110 |\
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HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
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HRCW_CS10PC01 | HRCW_MODCK_H0101 \
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)
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xF0F00000
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#ifdef CONFIG_SYS_REV_B
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#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
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#endif /* CONFIG_SYS_REV_B */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
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HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_BCR 0xA01C0000
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined (CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CONFIG_SYS_SCCR SCCR_DFBRG01
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*-----------------------------------------------------------------------
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSize Device
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* ---- --- ------- ----------------------------- ------
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* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
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* 1 60x SDRAM 64 bit SDRAM
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* 2 Local SDRAM 32 bit SDRAM
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*/
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#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
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controller, rely on initialisation
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performed by the Interphase boot firmware.
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*/
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#define CONFIG_SYS_OR0_PRELIM 0xFE000882
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#ifdef CONFIG_SYS_REV_B
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
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#else /* Rev. D */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
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#endif /* CONFIG_SYS_REV_B */
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#define CONFIG_SYS_MPTPR 0x7F00
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/* Please note that 60x SDRAM MUST start at 0 */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_60x_BR 0x00000041
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#define CONFIG_SYS_60x_OR 0xF0002CD0
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#define CONFIG_SYS_PSDMR 0x0049929A
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#define CONFIG_SYS_PSRT 0x07
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#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
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#define CONFIG_SYS_LOC_BR 0x00001861
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#define CONFIG_SYS_LOC_OR 0xFF803280
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#define CONFIG_SYS_LSDMR 0x8285A552
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#define CONFIG_SYS_LSRT 0x07
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#endif /* __CONFIG_H */
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