upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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343 lines
9.7 KiB
343 lines
9.7 KiB
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_PM520 1 /* ... on PM520 board */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_MII 1
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#define CONFIG_EEPRO100 1
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#undef CONFIG_NS8382X
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/* Partitions */
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#define CONFIG_DOS_PARTITION
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/* USB */
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#if 1
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_PCI
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=pm520\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk30/ppc_82xx\0" \
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"bootfile=/tftpboot/PM520/uImage\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#define CONFIG_SYS_DOC_BASE 0xE0000000
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#define CONFIG_SYS_DOC_SIZE 0x00100000
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#if defined(CONFIG_BOOT_ROM)
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/*
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* Flash configuration (8,16 or 32 MB)
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* TEXT base always at 0xFFF00000
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* ENV_ADDR always at 0xFFF40000
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* FLASH_BASE at 0xFA000000 for 64 MB
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* 0xFC000000 for 32 MB
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* 0xFD000000 for 16 MB
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* 0xFD800000 for 8 MB
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFA000000
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#define CONFIG_SYS_FLASH_SIZE 0x04000000
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#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
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#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
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#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
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#else
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/*
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* Flash configuration (8,16 or 32 MB)
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* TEXT base always at 0xFFF00000
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* ENV_ADDR always at 0xFFF40000
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* FLASH_BASE at 0xFC000000 for 64 MB
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* 0xFE000000 for 32 MB
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* 0xFF000000 for 16 MB
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* 0xFF800000 for 8 MB
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFC000000
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#define CONFIG_SYS_FLASH_SIZE 0x04000000
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#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
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#endif
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
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#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xf0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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/*
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* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
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*/
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/* #define CONFIG_MPC5xxx_FEC_MII10 */
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#if defined(CONFIG_BOOT_ROM)
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x00047800
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#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
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#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS1_CFG 0x0004FF00
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#else
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
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#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
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#define CONFIG_SYS_CS1_CFG 0x00047800
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#endif
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00005000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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