upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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443 lines
14 KiB
443 lines
14 KiB
/*
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* Copyright 2012-2013 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_A3M071 /* ... on A3M071 board */
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#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
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#define CONFIG_SPL_TARGET "u-boot-img.bin"
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
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#ifdef CONFIG_A4M2K
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#define CONFIG_HOSTNAME a4m2k
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#else
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#define CONFIG_HOSTNAME a3m071
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#endif
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#define CONFIG_BOOTCOUNT_LIMIT
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_DHCP
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_SERVERIP
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#define CONFIG_BOOTP_MAY_FAIL
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_SERVERIP
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#define CONFIG_NET_RETRY_COUNT 3
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#define CONFIG_CMD_LINK_LOCAL
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#define CONFIG_NETCONSOLE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_CMD_PING
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_MTD_PARTITIONS /* needed for UBI */
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=fc000000.flash"
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#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
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"128k(env1)," \
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"128k(env2)," \
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"128k(hwinfo)," \
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"1M(nvramsim)," \
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"128k(dtb)," \
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"5M(kernel)," \
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"128k(sysinfo)," \
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"7552k(root)," \
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"4M(app)," \
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"5376k(data)," \
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"8M(install)"
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#define CONFIG_LZO /* needed for UBI */
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#define CONFIG_RBTREE /* needed for UBI */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_FIT
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/* define for 66MHz speed - undef for 33MHz PCI clock speed */
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
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#else
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#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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/* maximum size of the flat tree (8K) */
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#define OF_FLAT_TREE_MAX_SIZE 8192
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
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/*
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* NOR flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfc000000
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#define CONFIG_SYS_FLASH_SIZE 0x02000000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_SYS_FLASH_LOCK_TOUT 5
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_FLASH_VERIFY
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xf0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MALLOC_LEN (4 << 20)
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC
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#define CONFIG_MPC5xxx_FEC_MII100
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#ifdef CONFIG_A4M2K
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#define CONFIG_PHY_ADDR 0x01
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#else
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#define CONFIG_PHY_ADDR 0x00
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#endif
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/*
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* GPIO configuration
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*/
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/*
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* GPIO-config depends on failsave-level
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* failsave 0 means just MPX-config, no digiboard, no fpga
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* 1 means digiboard ok
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* 2 means fpga ok
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*/
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
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#else
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/* for failsave-level 0 - full failsave */
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
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/* for failsave-level 1 - only digiboard ok */
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#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
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/* for failsave-level 2 - all ok */
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#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
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#endif
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#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
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#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
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#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
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#endif
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/*
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* Configuration matrix
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* MSB LSB
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* failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
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* failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
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* failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
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* || ||| || | ||| | | | |
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* || ||| || | ||| | | | | bit rev name
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* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
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* +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
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* ||| || | ||| | | | | 2 29 ALTs
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* +++-++--+---+++-+---+---+---+- 3 28 ALTs
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* ++-++--+---+++-+---+---+---+- 4 27 CS7
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* +-++--+---+++-+---+---+---+- 5 26 CS6
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* || | ||| | | | | 6 25 ATA
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* ++--+---+++-+---+---+---+- 7 24 ATA
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* +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
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* | ||| | | | | 9 22 IRDA
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* | ||| | | | | 10 21 IRDA
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* +---+++-+---+---+---+- 11 20 IRDA
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* ||| | | | | 12 19 Ether
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* ||| | | | | 13 18 Ether
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* ||| | | | | 14 17 Ether
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* +++-+---+---+---+- 15 16 Ether
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* ++-+---+---+---+- 16 15 PCI_DIS
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* +-+---+---+---+- 17 14 USB_SE
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* | | | | 18 13 USB
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* +---+---+---+- 19 12 USB
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* | | | 20 11 PSC3
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* | | | 21 10 PSC3
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* | | | 22 9 PSC3
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* +---+---+- 23 8 PSC3
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* | | 24 7 -
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* | | 25 6 PSC2
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* | | 26 5 PSC2
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* +---+- 27 4 PSC2
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* | 28 3 -
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* | 29 2 PSC1
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* | 30 1 PSC1
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* +- 31 0 PSC1
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*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024
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#else
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#define CONFIG_SYS_CBSIZE 256
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00100000
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#define CONFIG_SYS_MEMTEST_END 0x00f00000
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_LOOPW
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#ifdef CONFIG_A4M2K
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/* external MRAM */
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#define CONFIG_SYS_CS1_START 0xf1000000
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#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
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#endif
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#define CONFIG_SYS_CS2_START 0xe0000000
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#define CONFIG_SYS_CS2_SIZE 0x00100000
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/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
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#define CONFIG_SYS_CS3_START 0xE9000000
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_CS3_SIZE 0x00100000
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#else
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#define CONFIG_SYS_CS3_SIZE 0x00080000
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#endif
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/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
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#define CONFIG_SYS_CS3_CFG 0x0032B900
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#ifndef CONFIG_A4M2K
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/* Diagnosis Interface - see ticket #63 */
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#define CONFIG_SYS_CS4_START 0xEA000000
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#define CONFIG_SYS_CS4_SIZE 0x00000001
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/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
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#define CONFIG_SYS_CS4_CFG 0x0002B900
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#endif
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/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
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#define CONFIG_SYS_CS5_START 0xE8000000
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_CS5_SIZE 0x00100000
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#else
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#define CONFIG_SYS_CS5_SIZE 0x00010000
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#endif
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/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
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#define CONFIG_SYS_CS5_CFG 0x0032B900
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#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
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#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
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#define CONFIG_SYS_CS1_CFG 0x0008FD00
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#define CONFIG_SYS_CS2_CFG 0x0006F90C
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#else /* for pci_clk = 33 MHz */
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#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
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#define CONFIG_SYS_CS1_CFG 0x0001FB00
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#define CONFIG_SYS_CS2_CFG 0x0002F90C
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#endif
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#define CONFIG_SYS_CS_BURST 0x00000000
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/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
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/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
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/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
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#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*
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* Environment Configuration
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*/
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#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_SYS_AUTOLOAD "n"
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
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"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_SYS_OS_BASE 0xfc200000
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#define CONFIG_SYS_FDT_BASE 0xfc1e0000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"verify=no\0" \
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"loadaddr=200000\0" \
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"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
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"kernel_addr_r=1000000\0" \
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"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
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"fdt_addr_r=1800000\0" \
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"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
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"fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
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__stringify(CONFIG_HOSTNAME) ".dtb\0" \
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"rootpath=/opt/eldk-5.2.1/powerpc/" \
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"core-image-minimal-mtdutils-dropbear-generic\0" \
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"consoledev=ttyPSC0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"mtdargs=setenv bootargs root=/dev/mtdblock8 " \
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"rootfstype=squashfs,jffs2\0" \
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"addhost=setenv bootargs ${bootargs} " \
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"hostname=${hostname}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} " \
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"console=${consoledev},${baudrate}\0" \
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"flash_nfs=run nfsargs addip addtty addmtd addhost;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"flash_mtd=run mtdargs addip addtty addmtd addhost;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"flash_self=run ramargs addip addtty addmtd addhost;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"run nfsargs addip addtty addmtd addhost;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
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"/u-boot-img.bin\0" \
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"update=protect off fc000000 fc07ffff;" \
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"era fc000000 fc07ffff;" \
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"cp.b ${loadaddr} fc000000 ${filesize}\0" \
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"upd=run load;run update\0" \
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"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
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"run mtdargs addip addtty addmtd addhost;" \
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"fdt addr 1800000;fdt boardsetup;fdt chosen;" \
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"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
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"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
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"erase fc200000 fc6fffff;" \
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"cp.b 1000000 fc200000 ${filesize}" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_mtd"
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/*
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* SPL related defines
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*/
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#define CONFIG_SPL
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NOR_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0xfc000000
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#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
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#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
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#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
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#define CONFIG_SPL_SERIAL_SUPPORT
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/* Place BSS for SPL near end of SDRAM */
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#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
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#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
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#define CONFIG_SPL_OS_BOOT
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#define CONFIG_SPL_ENV_SUPPORT
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/* Place patched DT blob (fdt) at this address */
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
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/* Settings for real U-Boot to be loaded from NOR flash */
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#ifndef __ASSEMBLY__
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extern char __spl_flash_end[];
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#endif
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#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
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#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
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#define CONFIG_SYS_UBOOT_START 0x1000100
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#endif /* __CONFIG_H */
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