upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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402 lines
11 KiB
402 lines
11 KiB
/*
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* (C) Copyright 2013
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* based on P1022DS.h
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_SDCARD
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#define CONFIG_RAMBOOT_SDCARD
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH
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#endif
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/* High Level Configuration Options */
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#define CONFIG_CONTROLCENTERD
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_SYS_CLK_FREQ 66666600
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#define CONFIG_DDR_CLK_FREQ 66666600
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#define CONFIG_SYS_RAMBOOT
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#ifdef CONFIG_TRAILBLAZER
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#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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/*
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* Config the L2 Cache
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*/
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
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#else
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#endif
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#else /* CONFIG_TRAILBLAZER */
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#endif /* CONFIG_TRAILBLAZER */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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/*
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* Memory map
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*
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* 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
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* 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
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* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
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*
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* Localbus non-cacheable
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* 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
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* 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#ifdef CONFIG_TRAILBLAZER
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/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
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#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
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#else
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#endif
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE 1024
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_SYS_MEMTEST_START 0x00000000
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#define CONFIG_SYS_MEMTEST_END 0x3fffffff
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#ifdef CONFIG_TRAILBLAZER
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#define CONFIG_SPD_EEPROM
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#define SPD_EEPROM_ADDRESS 0x52
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/*#define CONFIG_FSL_DDR_INTERACTIVE*/
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#endif
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_ELBC_BASE 0xe0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
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#endif
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#define CONFIG_UART_BR_PRELIM \
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(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
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#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
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#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
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#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
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#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
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#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#ifndef CONFIG_TRAILBLAZER
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#endif
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#define CONFIG_PCA9698 /* NXP PCA9698 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#ifndef CONFIG_TRAILBLAZER
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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#endif
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/*
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* MMC
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*/
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#ifndef CONFIG_TRAILBLAZER
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/*
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* Video
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*/
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#define CONFIG_FSL_DIU_FB
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#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/*
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* SATA
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*/
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#define CONFIG_LBA48
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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/*
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* Ethernet
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*/
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSECV2
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#endif /* CONFIG_TRAILBLAZER */
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/*
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* Environment
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*/
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#if defined(CONFIG_TRAILBLAZER)
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#elif defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#elif defined(CONFIG_RAMBOOT_SDCARD)
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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/*
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* Command line configuration.
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#ifndef CONFIG_TRAILBLAZER
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/*
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* Board initialisation callbacks
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*/
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_LAST_STAGE_INIT
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#else /* CONFIG_TRAILBLAZER */
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_LAST_STAGE_INIT
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#endif /* CONFIG_TRAILBLAZER */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#ifdef CONFIG_TRAILBLAZER
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mp_holdoff=1\0"
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#else
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#define CONFIG_HOSTNAME controlcenterd
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot && " \
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"protect off $ubootaddr +$filesize && " \
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"erase $ubootaddr +$filesize && " \
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"cp.b $loadaddr $ubootaddr $filesize && " \
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"protect on $ubootaddr +$filesize && " \
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"cmp.b $loadaddr $ubootaddr $filesize\0" \
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"consoledev=ttyS1\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"fdtfile=controlcenterd.dtb\0" \
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"bdev=sda3\0"
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/* these are used and NUL-terminated in env_default.h */
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#endif /* CONFIG_TRAILBLAZER */
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#endif
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