upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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130 lines
3.0 KiB
130 lines
3.0 KiB
/*
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* iPAQ h2200 board configuration
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*
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* Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MACH_TYPE MACH_TYPE_H2200
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#define CONFIG_CPU_PXA25X 1
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
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#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
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#define CONFIG_ENV_SIZE 0x00040000
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
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/*
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* iPAQ 1st stage bootloader loads 2nd stage bootloader
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* at address 0xa0040000 but bootloader requires header
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* which is 0x1000 long.
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*
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* --- Header begin ---
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* .word 0xea0003fe ; b 0x1000
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*
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* .org 0x40
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* .ascii "ECEC"
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*
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* .org 0x1000
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* --- Header end ---
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*/
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/*
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* Static chips
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*/
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#define CONFIG_SYS_MSC0_VAL 0x246c7ffc
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#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
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#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000000
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#define CONFIG_SYS_MCMEM0_VAL 0x00000000
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#define CONFIG_SYS_MCMEM1_VAL 0x00000000
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#define CONFIG_SYS_MCATT0_VAL 0x00000000
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#define CONFIG_SYS_MCATT1_VAL 0x00000000
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#define CONFIG_SYS_MCIO0_VAL 0x00000000
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#define CONFIG_SYS_MCIO1_VAL 0x00000000
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00040004
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#define CONFIG_SYS_MDREFR_VAL 0x0099E018
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#define CONFIG_SYS_MDCNFG_VAL 0x01C801CB
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_PSSR_VAL 0x00000000
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#define CONFIG_SYS_CKEN 0x00004840
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#define CONFIG_SYS_CCCR 0x00000161
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/*
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* GPIOs
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x01000000
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#define CONFIG_SYS_GPSR1_VAL 0x00000000
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#define CONFIG_SYS_GPSR2_VAL 0x00010000
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000000
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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#define CONFIG_SYS_GPDR0_VAL 0xF7E38C00
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#define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83
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#define CONFIG_SYS_GPDR2_VAL 0x000157FF
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#define CONFIG_SYS_GAFR0_L_VAL 0x80401000
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#define CONFIG_SYS_GAFR0_U_VAL 0x00000112
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#define CONFIG_SYS_GAFR1_L_VAL 0x600A9550
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#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
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#define CONFIG_SYS_GAFR2_L_VAL 0x20000000
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#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
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/*
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* Serial port
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*/
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#define CONFIG_FFUART
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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/* Monitor Command Prompt */
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#define CONFIG_USB_DEV_PULLUP_GPIO 33
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/* USB VBUS GPIO 3 */
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#define CONFIG_BOOTCOMMAND \
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"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
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"if bootp ; then setenv downloaded 1 ; fi ; done ; " \
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"source :script ; " \
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"bootm ; "
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#define CONFIG_USB_GADGET_PXA2XX
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#define CONFIG_USB_ETH_SUBSET
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#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#endif /* __CONFIG_H */
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