upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
2.1 KiB
70 lines
2.1 KiB
/*
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* Configuation settings for the Hitachi Solution Engine 7750
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MS7750SE_H
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#define __MS7750SE_H
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#define CONFIG_CPU_SH7750 1
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/* #define CONFIG_CPU_SH7751 1 */
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/* #define CONFIG_CPU_TYPE_R 1 */
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#define __LITTLE_ENDIAN__ 1
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Command line configuration.
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*/
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#define CONFIG_CONS_SCIF1 1
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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/* NOR Flash */
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/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
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* Flash memory banks
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*/
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#define CONFIG_SYS_MAX_FLASH_SECT 142
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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#define CONFIG_SYS_RX_ETH_BUFFER (8)
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __MS7750SE_H */
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