upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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81 lines
2.1 KiB
81 lines
2.1 KiB
/*
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* Configuration settings for the SAMA5D4EK board.
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*
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* Copyright (C) 2014 Atmel
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "at91-sama5_common.h"
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x218000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x80000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#endif
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x200000
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#define CONFIG_SPL_MAX_SIZE 0x18000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#elif CONFIG_SPI_BOOT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
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#elif CONFIG_NAND_BOOT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#endif
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#define CONFIG_PMECC_CAP 8
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 224
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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