upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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135 lines
4.4 KiB
135 lines
4.4 KiB
/*
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* Configuation settings for the Renesas Technology R0P7785LC0011RL board
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*
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* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SH7785LCR_H
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#define __SH7785LCR_H
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#define CONFIG_CPU_SH7785 1
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootdevice=0:1\0" \
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"usbload=usb reset;usbboot;usb stop;bootm\0"
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#if defined(CONFIG_SH_32BIT)
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/* 0x40000000 - 0x47FFFFFF does not use */
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#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
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#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
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#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
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#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
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#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
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#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
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#define SH7785LCR_USB_BASE (0xa6000000)
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#else
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#define SH7785LCR_SDRAM_BASE (0x08000000)
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#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
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#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
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#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
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#define SH7785LCR_USB_BASE (0xb4000000)
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#endif
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_CONS_SCIF1 1
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#define CONFIG_SCIF_EXT_CLOCK 1
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#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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(SH7785LCR_SDRAM_SIZE) - \
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4 * 1024 * 1024)
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#undef CONFIG_SYS_ALT_MEMTEST
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
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(0 * SH7785LCR_FLASH_BANK_SIZE) }
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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#undef CONFIG_SYS_FLASH_PROTECTION
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* R8A66597 */
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#define CONFIG_USB_R8A66597_HCD
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#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
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#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
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#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
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#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
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/* PCI Controller */
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#define CONFIG_SH4_PCI
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#define CONFIG_SH7780_PCI
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#if defined(CONFIG_SH_32BIT)
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#define CONFIG_SH7780_PCI_LSR 0x1ff00001
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#define CONFIG_SH7780_PCI_LAR 0x5f000000
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#define CONFIG_SH7780_PCI_BAR 0x5f000000
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#else
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#define CONFIG_SH7780_PCI_LSR 0x07f00001
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#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
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#endif
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
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#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
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#if defined(CONFIG_SH_32BIT)
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#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
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#else
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#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
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#endif
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#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
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/* ENV setting */
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (256 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* Board Clock */
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/* The SCIF used external clock. system clock only used timer. */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __SH7785LCR_H */
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