upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.5 KiB
61 lines
1.5 KiB
/*
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* Copyright (C) STMicroelectronics SA 2017
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* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Configuration of the external SDRAM memory
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_RAM_FREQ_DIV 2
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#define CONFIG_SYS_RAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
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#define CONFIG_SYS_LOAD_ADDR 0x00400000
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#define CONFIG_LOADADDR 0x00400000
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#define CONFIG_SYS_MAX_FLASH_SECT 12
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_ENV_OFFSET (256 << 10)
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#define CONFIG_ENV_SECT_SIZE (128 << 10)
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#define CONFIG_ENV_SIZE (8 << 10)
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#define CONFIG_STM32_FLASH
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#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
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#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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#define CONFIG_BOOTCOMMAND \
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"run boot_sd"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
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/*
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* Command line configuration.
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*/
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#endif /* __CONFIG_H */
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