upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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440 lines
10 KiB
440 lines
10 KiB
/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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#include <pci.h>
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#include <405gp_pci.h>
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#include "pci405.h"
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
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unsigned long fpga_done_state(void);
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unsigned long fpga_init_state(void);
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#if 0
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#define FPGA_DEBUG
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#endif
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/* predefine these here */
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#define FPGA_DONE_STATE (fpga_done_state())
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#define FPGA_INIT_STATE (fpga_init_state())
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
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#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
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#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
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#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
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int board_revision(void)
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{
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unsigned long cntrl0Reg;
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unsigned long value;
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/*
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* Get version of PCI405 board from GPIO's
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*/
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/*
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* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x03000000);
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
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udelay(1000); /* wait some time before reading input */
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value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
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/*
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* Restore GPIO settings
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*/
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mtdcr(cntrl0, cntrl0Reg);
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switch (value) {
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case 0x00100200:
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/* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
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return 1;
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case 0x00000200:
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/* CS2==0 && IRQ5==1 -> version 1.2 */
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return 2;
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case 0x00000000:
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/* CS2==0 && IRQ5==0 -> version 1.3 */
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return 3;
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#if 0 /* not yet manufactured ! */
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case 0x00100000:
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/* CS2==1 && IRQ5==0 -> version 1.4 */
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return 4;
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#endif
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default:
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/* should not be reached! */
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return 0;
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}
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}
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unsigned long fpga_done_state(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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if (gd->board_type < 2) {
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return FPGA_DONE_STATE_V11;
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} else {
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return FPGA_DONE_STATE_V12;
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}
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}
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unsigned long fpga_init_state(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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if (gd->board_type < 2) {
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return FPGA_INIT_STATE_V11;
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} else {
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return FPGA_INIT_STATE_V12;
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}
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}
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int board_early_init_f (void)
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{
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unsigned long cntrl0Reg;
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/*
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* First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
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*/
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
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out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
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out32(GPIO0_OR, 0); /* pull prg low */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* Setup GPIO pins (IRQ4/GPIO21 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x00008000);
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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*/
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mtdcr(cntrl0, cntrl0Reg | 0x00300000);
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned int *ptr;
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unsigned int *magic;
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/*
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* On PCI-405 the environment is saved in eeprom!
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* FPGA can be gzip compressed (malloc) and booted this late.
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*/
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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/*
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* Check if magic for pci reconfig is written
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*/
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magic = (unsigned int *)0x00000004;
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if (*magic == PCI_RECONFIG_MAGIC) {
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/*
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* Rewrite pci config regs (only after soft-reset with magic set)
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*/
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ptr = (unsigned int *)PCI_REGS_ADDR;
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if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
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puts("Restoring PCI Configurations Regs!\n");
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ptr = (unsigned int *)PCI_REGS_ADDR + 1;
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for (i=0; i<0x40; i+=4) {
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pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
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}
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}
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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*magic = 0; /* clear pci reconfig magic again */
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}
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#if 1 /* test-only */
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/*
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* Decrease PLB latency timeout and reduce priority of the PCI bridge master
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*/
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#define PCI0_BRDGOPT1 0x4a
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pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
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/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
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#define plb0_acr 0x87
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/*
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* Enable fairness and high bus utilization
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*/
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mtdcr(plb0_acr, 0x98000000);
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#if 0 /* test-only */
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printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
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/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
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mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
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#endif
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/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
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#endif
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free(dst);
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming PCI405");
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} else {
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puts (str);
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}
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gd->board_type = board_revision();
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printf(" (Rev 1.%ld", gd->board_type);
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if (gd->board_type >= 2) {
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unsigned long cntrl0Reg;
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unsigned long value;
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/*
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* Setup GPIO pins (Trace/GPIO1 to GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
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udelay(1000); /* wait some time before reading input */
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value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
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if (value) {
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puts(", 33 MHz PCI");
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} else {
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puts(", 66 Mhz PCI");
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}
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}
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puts(")\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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#if 0 /* test-only: all PCI405 version must report 16mb */
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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#else
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return (16*1024*1024);
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#endif
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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int wpeeprom(int wp)
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{
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int wp_state = wp;
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volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
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if (wp == 1) {
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*uart1_mcr &= ~0x02;
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} else if (wp == 0) {
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*uart1_mcr |= 0x02;
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} else {
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if (*uart1_mcr & 0x02) {
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wp_state = 0;
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} else {
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wp_state = 1;
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}
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}
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return wp_state;
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}
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int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int wp = -1;
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if (argc >= 2) {
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if (argv[1][0] == '1') {
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wp = 1;
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} else if (argv[1][0] == '0') {
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wp = 0;
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}
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}
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wp = wpeeprom(wp);
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printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
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return 0;
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}
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U_BOOT_CMD(
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wpeeprom, 2, 1, do_wpeeprom,
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"wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
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"wpeeprom\n"
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" - check I2C EEPROM write protection state\n"
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"wpeeprom 1\n"
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" - enable I2C EEPROM write protection\n"
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"wpeeprom 0\n"
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" - disable I2C EEPROM write protection\n"
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);
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