upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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547 lines
16 KiB
547 lines
16 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* esd vme8349 U-Boot configuration file
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* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
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*
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* (C) Copyright 2006-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* reinhard.arlt@esd-electronics.de
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* Based on the MPC8349EMDS config.
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*/
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/*
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* vme8349 board configuration file.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Top level Makefile configuration choices
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*/
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#ifdef CONFIG_CADDY2
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#define VME_CADDY2
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#endif
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC834x 1 /* MPC834x family */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
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/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
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#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
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#define CONFIG_PCI_66M
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#ifdef CONFIG_PCI_66M
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#else
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#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#ifdef CONFIG_PCI_66M
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
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#else
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#define CONFIG_SYS_CLK_FREQ 33000000
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#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
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#endif
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#endif
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#define CONFIG_SYS_IMMR 0xE0000000
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00100000
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/*
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* DDR Setup
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*/
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM
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#define SPD_EEPROM_ADDRESS 0x54
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#define CONFIG_SYS_READ_SPD vme8349_read_spd
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#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
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/*
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* 32-bit data path mode.
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*
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* Please note that using this mode for devices with the real density of 64-bit
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* effectively reduces the amount of available memory due to the effect of
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* wrapping around while translating address to row/columns, for example in the
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* 256MB module the upper 128MB get aliased with contents of the lower
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* 128MB); normally this define should be used for devices with real 32-bit
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* data path.
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*/
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#undef CONFIG_DDR_32BIT
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
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#define CONFIG_DDR_2T_TIMING
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#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x80080001 */
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#ifdef VME_CADDY2
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#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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BR_PS_16 | /* 16bit */ \
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BR_MS_GPCM | /* MSEL = GPCM */ \
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BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_GPCM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xffc06ff7 */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
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#else
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#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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BR_PS_16 | /* 16bit */ \
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BR_MS_GPCM | /* MSEL = GPCM */ \
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BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_GPCM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xf8006ff7 */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
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#endif
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/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
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#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
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| BR_PS_32 \
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| BR_MS_GPCM \
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| BR_V)
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/* 0xF0001801 */
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
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| OR_GPCM_SETA)
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/* 0xfffc0208 */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: no DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
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#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
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/* TSEC */
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
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#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
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#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
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#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
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#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
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#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
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#if defined(CONFIG_PCI)
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#define PCI_64BIT
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#define PCI_ONE_PCI1
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#if defined(PCI_64BIT)
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#undef PCI_ALL_PCI1
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#undef PCI_TWO_PCI1
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#undef PCI_ONE_PCI1
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#endif
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xFIXME
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#define PCI_ENET0_MEMADDR 0xFIXME
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#define PCI_IDSEL_NUMBER 0xFIXME
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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/*
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* TSEC configuration
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*/
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_GMII /* MII PHY management */
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#define CONFIG_TSEC1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_PHY_M88E1111
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#define TSEC1_PHY_ADDR 0x08
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#define TSEC2_PHY_ADDR 0x10
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#define CONFIG_SYS_RTC_BUS_NUM 0x01
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#define CONFIG_SYS_I2C_RTC_ADDR 0x32
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#define CONFIG_RTC_RX8025
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/* Pass Ethernet MAC to VxWorks */
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#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
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#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_CSB_TO_CLKIN |\
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HRCWL_VCO_1X2 |\
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HRCWL_CORE_TO_CSB_2X1)
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#if defined(PCI_64BIT)
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_64_BIT_PCI |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCI2_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII)
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#else
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_32_BIT_PCI |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCI2_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII)
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#endif
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/* System IO Config */
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#define CONFIG_SYS_SICRH 0
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#define CONFIG_SYS_SICRL SICRL_LDP_A
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_SYS_GPIO1_PRELIM
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#define CONFIG_SYS_GPIO1_DIR 0x00100000
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#define CONFIG_SYS_GPIO1_DAT 0x00100000
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#define CONFIG_SYS_GPIO2_PRELIM
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#define CONFIG_SYS_GPIO2_DIR 0x78900000
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#define CONFIG_SYS_GPIO2_DAT 0x70100000
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#define CONFIG_HIGH_BATS /* High BATs supported */
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/* DDR @ 0x00000000 */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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/* PCI @ 0x80000000 */
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#else
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#define CONFIG_SYS_IBAT1L (0)
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#define CONFIG_SYS_IBAT1U (0)
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#define CONFIG_SYS_IBAT2L (0)
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#define CONFIG_SYS_IBAT2U (0)
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#endif
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#ifdef CONFIG_MPC83XX_PCI2
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
|
|
#else
|
|
#define CONFIG_SYS_IBAT3L (0)
|
|
#define CONFIG_SYS_IBAT3U (0)
|
|
#define CONFIG_SYS_IBAT4L (0)
|
|
#define CONFIG_SYS_IBAT4U (0)
|
|
#endif
|
|
|
|
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
|
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
|
|
BATU_VS | BATU_VP)
|
|
|
|
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
|
|
#if (CONFIG_SYS_DDR_SIZE == 512)
|
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
|
|
BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
|
|
BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#else
|
|
#define CONFIG_SYS_IBAT7L (0)
|
|
#define CONFIG_SYS_IBAT7U (0)
|
|
#endif
|
|
|
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_HAS_ETH0
|
|
#define CONFIG_HAS_ETH1
|
|
#endif
|
|
|
|
#define CONFIG_HOSTNAME "VME8349"
|
|
#define CONFIG_ROOTPATH "/tftpboot/rootfs"
|
|
#define CONFIG_BOOTFILE "uImage"
|
|
|
|
#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"hostname=vme8349\0" \
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
":${hostname}:${netdev}:off panic=1\0" \
|
|
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
|
"flash_nfs=run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr}\0" \
|
|
"flash_self=run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
|
"bootm\0" \
|
|
"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
|
|
"update=protect off fff00000 fff3ffff; " \
|
|
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
|
|
"upd=run load update\0" \
|
|
"fdtaddr=780000\0" \
|
|
"fdtfile=vme8349.dtb\0" \
|
|
""
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
"$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
|
|
#ifndef __ASSEMBLY__
|
|
int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
|
|
unsigned char *buffer, int len);
|
|
#endif
|
|
|
|
#endif /* __CONFIG_H */
|
|
|