upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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413 lines
12 KiB
413 lines
12 KiB
/*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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* Roland Dreier <rolandd@cisco.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <ppc4xx.h>
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#ifndef __4XX_PCIE_H
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#define __4XX_PCIE_H
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#define DCRN_SDR0_CFGADDR 0x00e
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#define DCRN_SDR0_CFGDATA 0x00f
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#if defined(CONFIG_440SPE)
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#define CFG_PCIE_NR_PORTS 3
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#define CFG_PCIE_ADDR_HIGH 0x0000000d
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#define DCRN_PCIE0_BASE 0x100
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#define DCRN_PCIE1_BASE 0x120
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#define DCRN_PCIE2_BASE 0x140
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#define PCIE0_SDR 0x300
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#define PCIE1_SDR 0x340
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#define PCIE2_SDR 0x370
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define CFG_PCIE_NR_PORTS 2
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#define CFG_PCIE_ADDR_HIGH 0x0000000d
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#define DCRN_PCIE0_BASE 0x100
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#define DCRN_PCIE1_BASE 0x120
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#define PCIE0_SDR 0x300
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#define PCIE1_SDR 0x340
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#endif
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#if defined(CONFIG_405EX)
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#define CFG_PCIE_NR_PORTS 2
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#define CFG_PCIE_ADDR_HIGH 0x00000000
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#define DCRN_PCIE0_BASE 0x040
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#define DCRN_PCIE1_BASE 0x060
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#define PCIE0_SDR 0x400
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#define PCIE1_SDR 0x440
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#endif
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#define PCIE0 DCRN_PCIE0_BASE
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#define PCIE1 DCRN_PCIE1_BASE
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#define PCIE2 DCRN_PCIE2_BASE
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#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
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#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
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#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
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#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
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#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
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#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
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#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
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#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
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#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
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#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
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#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
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#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
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#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
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#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
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#define DCRN_PEGPL_CFG(base) (base + 0x16)
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/*
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* System DCRs (SDRs)
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*/
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#define PESDR0_PLLLCT1 0x03a0
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#define PESDR0_PLLLCT2 0x03a1
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#define PESDR0_PLLLCT3 0x03a2
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/* common regs, at for all 4xx with PCIe core */
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#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
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#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
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#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
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#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
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#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
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#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
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#if defined(CONFIG_440SPE)
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#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
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#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
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#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
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#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
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#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
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#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
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#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
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#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
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#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
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#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
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#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
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#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
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#define PESDR0_UTLSET1 0x0300
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#define PESDR0_UTLSET2 0x0301
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#define PESDR0_DLPSET 0x0302
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#define PESDR0_LOOP 0x0303
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#define PESDR0_RCSSET 0x0304
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#define PESDR0_RCSSTS 0x0305
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#define PESDR0_HSSL0SET1 0x0306
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#define PESDR0_HSSL0SET2 0x0307
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#define PESDR0_HSSL0STS 0x0308
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#define PESDR0_HSSL1SET1 0x0309
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#define PESDR0_HSSL1SET2 0x030a
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#define PESDR0_HSSL1STS 0x030b
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#define PESDR0_HSSL2SET1 0x030c
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#define PESDR0_HSSL2SET2 0x030d
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#define PESDR0_HSSL2STS 0x030e
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#define PESDR0_HSSL3SET1 0x030f
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#define PESDR0_HSSL3SET2 0x0310
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#define PESDR0_HSSL3STS 0x0311
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#define PESDR0_HSSL4SET1 0x0312
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#define PESDR0_HSSL4SET2 0x0313
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#define PESDR0_HSSL4STS 0x0314
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#define PESDR0_HSSL5SET1 0x0315
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#define PESDR0_HSSL5SET2 0x0316
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#define PESDR0_HSSL5STS 0x0317
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#define PESDR0_HSSL6SET1 0x0318
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#define PESDR0_HSSL6SET2 0x0319
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#define PESDR0_HSSL6STS 0x031a
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#define PESDR0_HSSL7SET1 0x031b
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#define PESDR0_HSSL7SET2 0x031c
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#define PESDR0_HSSL7STS 0x031d
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#define PESDR0_HSSCTLSET 0x031e
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#define PESDR0_LANE_ABCD 0x031f
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#define PESDR0_LANE_EFGH 0x0320
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#define PESDR1_UTLSET1 0x0340
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#define PESDR1_UTLSET2 0x0341
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#define PESDR1_DLPSET 0x0342
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#define PESDR1_LOOP 0x0343
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#define PESDR1_RCSSET 0x0344
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#define PESDR1_RCSSTS 0x0345
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#define PESDR1_HSSL0SET1 0x0346
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#define PESDR1_HSSL0SET2 0x0347
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#define PESDR1_HSSL0STS 0x0348
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#define PESDR1_HSSL1SET1 0x0349
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#define PESDR1_HSSL1SET2 0x034a
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#define PESDR1_HSSL1STS 0x034b
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#define PESDR1_HSSL2SET1 0x034c
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#define PESDR1_HSSL2SET2 0x034d
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#define PESDR1_HSSL2STS 0x034e
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#define PESDR1_HSSL3SET1 0x034f
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#define PESDR1_HSSL3SET2 0x0350
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#define PESDR1_HSSL3STS 0x0351
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#define PESDR1_HSSCTLSET 0x0352
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#define PESDR1_LANE_ABCD 0x0353
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#define PESDR2_UTLSET1 0x0370
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#define PESDR2_UTLSET2 0x0371
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#define PESDR2_DLPSET 0x0372
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#define PESDR2_LOOP 0x0373
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#define PESDR2_RCSSET 0x0374
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#define PESDR2_RCSSTS 0x0375
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#define PESDR2_HSSL0SET1 0x0376
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#define PESDR2_HSSL0SET2 0x0377
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#define PESDR2_HSSL0STS 0x0378
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#define PESDR2_HSSL1SET1 0x0379
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#define PESDR2_HSSL1SET2 0x037a
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#define PESDR2_HSSL1STS 0x037b
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#define PESDR2_HSSL2SET1 0x037c
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#define PESDR2_HSSL2SET2 0x037d
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#define PESDR2_HSSL2STS 0x037e
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#define PESDR2_HSSL3SET1 0x037f
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#define PESDR2_HSSL3SET2 0x0380
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#define PESDR2_HSSL3STS 0x0381
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#define PESDR2_HSSCTLSET 0x0382
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#define PESDR2_LANE_ABCD 0x0383
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#elif defined(CONFIG_405EX)
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#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
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#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
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#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
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#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
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#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
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#define PESDR0_UTLSET1 0x0400
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#define PESDR0_UTLSET2 0x0401
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#define PESDR0_DLPSET 0x0402
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#define PESDR0_LOOP 0x0403
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#define PESDR0_RCSSET 0x0404
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#define PESDR0_RCSSTS 0x0405
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#define PESDR0_PHYSET1 0x0406
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#define PESDR0_PHYSET2 0x0407
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#define PESDR0_BIST 0x0408
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#define PESDR0_LPB 0x040B
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#define PESDR0_PHYSTA 0x040C
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#define PESDR1_UTLSET1 0x0440
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#define PESDR1_UTLSET2 0x0441
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#define PESDR1_DLPSET 0x0442
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#define PESDR1_LOOP 0x0443
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#define PESDR1_RCSSET 0x0444
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#define PESDR1_RCSSTS 0x0445
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#define PESDR1_PHYSET1 0x0446
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#define PESDR1_PHYSET2 0x0447
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#define PESDR1_BIST 0x0448
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#define PESDR1_LPB 0x044B
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#define PESDR1_PHYSTA 0x044C
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#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
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#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
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#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
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#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
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#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
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#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
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#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
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#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
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#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
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#define PESDR0_OBS 0x0311 /* PE0 observation register */
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#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
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#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
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#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
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#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
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#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
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#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
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#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
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#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
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#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
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#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
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#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
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#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
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#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
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#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
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#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
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#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
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#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
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#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
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#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
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#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
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#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
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#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
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#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
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#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
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#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
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#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
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#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
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#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
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#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
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#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
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#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
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#define PESDR1_OBS 0x0366 /* PE1 observation register */
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#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
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#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
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#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
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#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
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#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
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#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
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#endif
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/* SDR Bit Mappings */
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#define PESDRx_RCSSET_HLDPLB 0x10000000
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#define PESDRx_RCSSET_RSTGU 0x01000000
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#define PESDRx_RCSSET_RDY 0x00100000
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#define PESDRx_RCSSET_RSTDL 0x00010000
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#define PESDRx_RCSSET_RSTPYN 0x00001000
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#define PESDRx_RCSSTS_PLBIDL 0x10000000
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#define PESDRx_RCSSTS_HRSTRQ 0x01000000
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#define PESDRx_RCSSTS_PGRST 0x00100000
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#define PESDRx_RCSSTS_VC0ACT 0x00010000
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#define PESDRx_RCSSTS_BMEN 0x00000100
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/*
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* UTL register offsets
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*/
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#define PEUTL_PBCTL 0x00
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#define PEUTL_PBBSZ 0x20
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#define PEUTL_OPDBSZ 0x68
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#define PEUTL_IPHBSZ 0x70
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#define PEUTL_IPDBSZ 0x78
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#define PEUTL_OUTTR 0x90
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#define PEUTL_INTR 0x98
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#define PEUTL_PCTL 0xa0
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#define PEUTL_RCSTA 0xb0
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#define PEUTL_RCIRQEN 0xb8
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/*
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* Config space register offsets
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*/
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#define PECFG_BAR0LMPA 0x210
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#define PECFG_BAR0HMPA 0x214
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#define PECFG_BAR1MPA 0x218
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#define PECFG_BAR2LMPA 0x220
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#define PECFG_BAR2HMPA 0x224
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#define PECFG_PIMEN 0x33c
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#define PECFG_PIM0LAL 0x340
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#define PECFG_PIM0LAH 0x344
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#define PECFG_PIM1LAL 0x348
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#define PECFG_PIM1LAH 0x34c
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#define PECFG_PIM01SAL 0x350
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#define PECFG_PIM01SAH 0x354
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#define PECFG_POM0LAL 0x380
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#define PECFG_POM0LAH 0x384
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#define SDR_READ(offset) ({\
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mtdcr(DCRN_SDR0_CFGADDR, offset); \
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mfdcr(DCRN_SDR0_CFGDATA);})
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#define SDR_WRITE(offset, data) ({\
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mtdcr(DCRN_SDR0_CFGADDR, offset); \
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mtdcr(DCRN_SDR0_CFGDATA,data);})
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#define GPL_DMER_MASK_DISA 0x02000000
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#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
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#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
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/*
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* Prototypes
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*/
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int ppc4xx_init_pcie(void);
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int ppc4xx_init_pcie_rootport(int port);
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int ppc4xx_init_pcie_endport(int port);
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void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
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int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
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int pcie_hose_scan(struct pci_controller *hose, int bus);
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/*
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* Function to determine root port or endport from env variable.
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*/
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static inline int is_end_point(int port)
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{
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char s[10], *tk;
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char *pcie_mode = getenv("pcie_mode");
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if (pcie_mode == NULL)
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return 0;
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strcpy(s, pcie_mode);
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tk = strtok(s, ":");
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switch (port) {
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case 0:
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if (tk != NULL) {
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if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
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return 1;
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else
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return 0;
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}
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else
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return 0;
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case 1:
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tk = strtok(NULL, ":");
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if (tk != NULL) {
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if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
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return 1;
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else
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return 0;
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}
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else
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return 0;
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case 2:
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tk = strtok(NULL, ":");
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if (tk != NULL)
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tk = strtok(NULL, ":");
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if (tk != NULL) {
|
|
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void mdelay(int n)
|
|
{
|
|
u32 ms = n;
|
|
|
|
while (ms--)
|
|
udelay(1000);
|
|
}
|
|
|
|
static inline u32 sdr_base(int port)
|
|
{
|
|
switch (port) {
|
|
default: /* to satisfy compiler */
|
|
case 0:
|
|
return PCIE0_SDR;
|
|
case 1:
|
|
return PCIE1_SDR;
|
|
#if CFG_PCIE_NR_PORTS > 2
|
|
case 2:
|
|
return PCIE2_SDR;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#endif /* __4XX_PCIE_H */
|
|
|