upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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233 lines
7.7 KiB
233 lines
7.7 KiB
/*
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* Rick Bronson <rick@efn.org>
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*
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* Configuation settings for the AT91RM9200DK board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
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#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CFG_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR_VAL 0x00000000
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#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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/* sdram */
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#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR_VAL 0xFFFF0000
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000080 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_BAUDRATE 115200
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/*
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* Hardware drivers
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*/
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#define CONFIG_DBGU
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_BOOTDELAY 3
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/* #define CONFIG_ENV_OVERWRITE 1 */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_DHCP
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_AUTOSCRIPT
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_MISC
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#undef CONFIG_CMD_LOADS
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
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#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
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#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
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/* the following are NOP's in our implementation */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII
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/* AC Characteristics */
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/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
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#define DATAFLASH_TCSS (0xC << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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#define CONFIG_HAS_DATAFLASH 1
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#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
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#define CFG_MAX_DATAFLASH_BANKS 2
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#define CFG_MAX_DATAFLASH_PAGES 16384
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#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
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#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#undef CFG_ENV_IS_IN_DATAFLASH
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#ifdef CFG_ENV_IS_IN_DATAFLASH
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#define CFG_ENV_OFFSET 0x20000
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#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
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#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
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#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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#else
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
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#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* CFG_ENV_IS_IN_DATAFLASH */
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
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#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
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#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
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#else
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#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
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#define CFG_U_BOOT_BASE PHYS_FLASH_1
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#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#define CFG_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
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#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_HZ 1000
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#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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