upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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262 lines
7.2 KiB
262 lines
7.2 KiB
/*
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* (C) Copyright 2007-2008 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/xilinx/ml401/xparameters.h"
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#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
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#define MICROBLAZE_V5 1
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#define CONFIG_ML401 1 /* ML401 Board */
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/* uart */
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#ifdef XILINX_UARTLITE_BASEADDR
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#define CONFIG_XILINX_UARTLITE
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#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
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#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
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#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#else
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#ifdef XILINX_UART16550_BASEADDR
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 4
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#define CONFIG_CONS_INDEX 1
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#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR
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#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600, 115200 }
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#endif
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#endif
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/* setting reset address */
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/*#define CFG_RESET_ADDRESS TEXT_BASE*/
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/* ethernet */
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#ifdef XILINX_EMAC_BASEADDR
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#define CONFIG_XILINX_EMAC 1
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#else
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#ifdef XILINX_EMACLITE_BASEADDR
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#define CONFIG_XILINX_EMACLITE 1
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#endif
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#endif
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#undef ET_DEBUG
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/* gpio */
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#ifdef XILINX_GPIO_BASEADDR
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#define CFG_GPIO_0 1
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#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
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#endif
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/* interrupt controller */
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#define CFG_INTC_0 1
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#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
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#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
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/* timer */
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#define CFG_TIMER_0 1
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#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
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#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
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#define FREQUENCE XILINX_CLOCK_FREQ
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#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
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#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
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/* FSL */
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/* #define CFG_FSL_2 */
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/* #define FSL_INTR_2 1 */
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/*
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* memory layout - Example
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* TEXT_BASE = 0x1200_0000;
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* CFG_SRAM_BASE = 0x1000_0000;
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* CFG_SRAM_SIZE = 0x0400_0000;
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*
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* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
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* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
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* CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
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*
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* 0x1000_0000 CFG_SDRAM_BASE
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* FREE
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* 0x1200_0000 TEXT_BASE
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* U-BOOT code
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* 0x1202_0000
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* FREE
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*
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* STACK
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* 0x13F7_F000 CFG_MALLOC_BASE
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* MALLOC_AREA 256kB Alloc
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* 0x11FB_F000 CFG_MONITOR_BASE
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* MONITOR_CODE 256kB Env
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* 0x13FF_F000 CFG_GBL_DATA_OFFSET
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* GLOBAL_DATA 4kB bd, gd
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* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
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*/
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/* ddr sdram - main memory */
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#define CFG_SDRAM_BASE XILINX_RAM_START
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#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
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#define CFG_MEMTEST_START CFG_SDRAM_BASE
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#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
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/* global pointer */
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#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
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/* start of global data */
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#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
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/* monitor code */
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#define SIZE 0x40000
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#define CFG_MONITOR_LEN SIZE
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#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
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#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_MALLOC_LEN SIZE
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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/* stack */
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#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
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/*#define RAMENV */
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#define FLASH
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#ifdef FLASH
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#define CFG_FLASH_BASE XILINX_FLASH_START
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#define CFG_FLASH_SIZE XILINX_FLASH_SIZE
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_FLASH_PROTECTION /* hardware flash protection */
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#ifdef RAMENV
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#define CFG_ENV_IS_NOWHERE 1
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#define CFG_ENV_SIZE 0x1000
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
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#else /* !RAMENV */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
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#define CFG_ENV_SIZE 0x40000
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#endif /* !RAMBOOT */
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#else /* !FLASH */
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/* ENV in RAM */
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#define CFG_NO_FLASH 1
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#define CFG_ENV_IS_NOWHERE 1
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#define CFG_ENV_SIZE 0x1000
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
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#define CFG_FLASH_PROTECTION /* hardware flash protection */
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#endif /* !FLASH */
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/* system ace */
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#ifdef XILINX_SYSACE_BASEADDR
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#define CONFIG_SYSTEMACE
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/* #define DEBUG_SYSTEMACE */
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#define SYSTEMACE_CONFIG_FPGA
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#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
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#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MFSL
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#define CONFIG_CMD_PING
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#if defined(CONFIG_SYSTEMACE)
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#endif
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#if defined(FLASH)
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMLS
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#define CONFIG_CMD_JFFS2
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#if !defined(RAMENV)
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_SAVES
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#endif
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#else
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#undef CONFIG_CMD_FLASH
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#endif
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#if defined(CONFIG_CMD_JFFS2)
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/* JFFS2 partitions */
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#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
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#define MTDIDS_DEFAULT "nor0=ml401-0"
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/* default mtd partition table */
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#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
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"256k(env),3m(kernel),1m(romfs),"\
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"1m(cramfs),-(jffs2)"
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#endif
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/* Miscellaneous configurable options */
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#define CFG_PROMPT "U-Boot-mONStR> "
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#define CFG_CBSIZE 512 /* size of console buffer */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
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#define CFG_MAXARGS 15 /* max number of command args */
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#define CFG_LONGHELP
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#define CFG_LOAD_ADDR 0x12000000 /* default load address */
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#define CONFIG_BOOTDELAY 30
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_HOSTNAME "ml401"
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_SERVERIP 192.168.0.5
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
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/* architecture dependent code */
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#define CFG_USR_EXCEP /* user exception */
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#define CFG_HZ 1000
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#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
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#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
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"nor0=ml401-0\0"\
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"mtdparts=mtdparts=ml401-0:"\
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"256k(u-boot),256k(env),3m(kernel),"\
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"1m(romfs),1m(cramfs),-(jffs2)\0"
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_OF_LIBFDT 1
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#endif /* __CONFIG_H */
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