upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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375 lines
12 KiB
375 lines
12 KiB
/*
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* Copyright 2011 Alex Dubov <oakad@yahoo.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Merury Computers MPQ101 board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_36BIT
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# define CONFIG_PHYS_64BIT
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE /* BOOKE */
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#define CONFIG_E500 /* BOOKE e500 family */
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#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
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#define CONFIG_MPC8548 /* MPC8548 specific */
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#define CONFIG_MPQ101 /* MPQ101 board specific */
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#define CONFIG_SYS_SRIO /* enable serial RapidIO */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_PANIC_HANG
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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# define CONFIG_ADDR_MAP
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# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
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#define CONFIG_SYS_CCSRBAR 0xe0000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_FSL_DDR2
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* Fixed 512MB DDR2 parameters */
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#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
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#define CONFIG_SYS_DDR_TIMING_3 0x00010000
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#define CONFIG_SYS_DDR_TIMING_0 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432
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#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
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#define CONFIG_SYS_DDR_TIMING_2 0x03984cce
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#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
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#define CONFIG_SYS_DDR_MODE_1 0x00400442
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#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x08200100
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#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
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#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */
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#define CONFIG_SYS_DDR_CONTROL2 0x04400000
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0ffffffc
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/*
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* RAM definitions
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
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/*
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* FLASH on the Local Bus
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* One bank, 128M, using the CFI driver.
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*/
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#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
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#ifdef CONFIG_PHYS_64BIT
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# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
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#else
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# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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/* 0xf8001801 */
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#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_32 | BR_V)
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/* 0xf8006ff7 */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
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| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
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| OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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* assume this is the AMD flash.
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*/
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#define CONFIG_ASSUME_AMD_FLASH
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/*
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* Environment parameters
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_USE_PPCENV
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#define ENV_IS_EMBEDDED
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
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#define CONFIG_ENV_SIZE 0x800
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/* Environment at the start of flash sector, before text. */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_TEXT_BASE 0xfffc0800
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#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds"
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/*
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* Cypress CY7C67200 USB controller on the Local Bus.
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* Not supported by u-boot at present.
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*/
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#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
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#ifdef CONFIG_PHYS_64BIT
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# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
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#else
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# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
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#endif
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/* 0xf0001001 */
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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/* fffff002 */
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#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
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| OR_GPCM_BCTLD | OR_GPCM_EHTR)
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/*
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* Serial Ports
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*/
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \
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19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/*
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* I2C buses and peripherals
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7f
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/* I2C RTC - M41T81 */
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#define CONFIG_RTC_M41T62
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 2000
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/* I2C EEPROM - 24C256 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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/*
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* RapidIO MMU
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*/
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#ifdef CONFIG_SYS_SRIO
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# define CONFIG_SRIO1
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# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
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# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
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# ifdef CONFIG_PHYS_64BIT
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# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
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# else
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# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
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# endif
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#endif
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/*
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* Ethernet
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*/
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#ifdef CONFIG_TSEC_ENET
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# define CONFIG_MII /* MII PHY management */
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# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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# define CONFIG_TSEC1
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# define CONFIG_TSEC1_NAME "eTSEC0"
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# define TSEC1_PHY_ADDR 0x10
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# define TSEC1_PHYIDX 0
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# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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# define CONFIG_TSEC2
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# define CONFIG_TSEC2_NAME "eTSEC1"
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# define TSEC2_PHY_ADDR 0x11
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# define TSEC2_PHYIDX 0
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# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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# define CONFIG_TSEC3
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# define CONFIG_TSEC3_NAME "eTSEC2"
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# define TSEC3_PHY_ADDR 0x12
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# define TSEC3_PHYIDX 0
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# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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# define CONFIG_TSEC4
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# define CONFIG_TSEC4_NAME "eTSEC3"
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# define TSEC4_PHY_ADDR 0x13
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# define TSEC4_PHYIDX 0
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# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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/* Options are: eTSEC[0-3] */
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# define CONFIG_ETHPRIME "eTSEC0"
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# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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#endif
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_JFFS2
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/*
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* Miscellaneous configurable options
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*/
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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#define CONFIG_FIT /* new uImage format support */
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */
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/* Console I/O Buffer Size */
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#ifdef CONFIG_CMD_KGDB
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# define CONFIG_SYS_CBSIZE 1024
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#else
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# define CONFIG_SYS_CBSIZE 256
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
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#ifdef CONFIG_CMD_KGDB
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# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Basic Environment Configuration
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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/*default location for tftp and bootm*/
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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#endif /* __CONFIG_H */
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