upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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443 lines
10 KiB
443 lines
10 KiB
/*
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* (C) Copyright 2000 - 2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Based ont the MPC5200 PSC driver.
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* Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
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*/
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/*
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* Minimal serial functions needed to use one of the PSC ports
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* as serial console interface.
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*/
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#include <common.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <serial.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_PSC_CONSOLE)
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static void fifo_init (volatile psc512x_t *psc)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 tfsize, rfsize;
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/* reset Rx & Tx fifo slice */
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out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
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out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
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/* disable Tx & Rx FIFO interrupts */
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out_be32(&psc->rfintmask, 0);
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out_be32(&psc->tfintmask, 0);
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switch (((u32)psc & 0xf00) >> 8) {
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case 0:
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tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
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rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
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break;
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case 1:
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tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
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rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
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break;
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case 2:
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tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
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rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
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break;
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case 3:
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tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
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rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
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break;
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case 4:
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tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
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rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
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break;
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case 5:
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tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
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rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
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break;
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case 6:
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tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
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rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
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break;
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case 7:
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tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
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rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
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break;
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case 8:
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tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
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rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
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break;
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case 9:
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tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
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rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
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break;
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case 10:
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tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
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rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
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break;
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case 11:
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tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
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rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
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break;
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default:
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return;
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}
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out_be32(&psc->tfsize, tfsize);
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out_be32(&psc->rfsize, rfsize);
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/* enable Tx & Rx FIFO slice */
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out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
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out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
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out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
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__asm__ volatile ("sync");
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}
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void serial_setbrg_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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unsigned long baseclk, div;
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unsigned long baudrate;
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char buf[16];
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char *br_env;
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baudrate = gd->baudrate;
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if (idx != CONFIG_PSC_CONSOLE) {
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/* Allows setting baudrate for other serial devices
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* on PSCx using environment. If not specified, use
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* the same baudrate as for console.
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*/
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sprintf(buf, "psc%d_baudrate", idx);
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br_env = getenv(buf);
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if (br_env)
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baudrate = simple_strtoul(br_env, NULL, 10);
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debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
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}
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/* calculate divisor for setting PSC CTUR and CTLR registers */
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baseclk = (gd->arch.ips_clk + 8) / 16;
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div = (baseclk + (baudrate / 2)) / baudrate;
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out_8(&psc->ctur, (div >> 8) & 0xff);
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out_8(&psc->ctlr, div & 0xff); /* set baudrate */
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}
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int serial_init_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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u32 reg;
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reg = in_be32(&im->clk.sccr[0]);
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out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
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fifo_init (psc);
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/* set MR register to point to MR1 */
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out_8(&psc->command, PSC_SEL_MODE_REG_1);
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/* disable Tx/Rx */
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out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
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/* choose the prescaler by 16 for the Tx/Rx clock generation */
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out_be16(&psc->psc_clock_select, 0xdd00);
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/* switch to UART mode */
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out_be32(&psc->sicr, 0);
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/* mode register points to mr1 */
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/* configure parity, bit length and so on in mode register 1*/
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out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
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/* now, mode register points to mr2 */
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out_8(&psc->mode, PSC_MODE_1_STOPBIT);
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/* set baudrate */
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serial_setbrg_dev(idx);
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/* disable all interrupts */
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out_be16(&psc->psc_imr, 0);
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/* reset and enable Rx/Tx */
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out_8(&psc->command, PSC_RST_RX);
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out_8(&psc->command, PSC_RST_TX);
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out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
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return 0;
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}
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int serial_uninit_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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u32 reg;
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out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
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reg = in_be32(&im->clk.sccr[0]);
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reg &= ~CLOCK_SCCR1_PSC_EN(idx);
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out_be32(&im->clk.sccr[0], reg);
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return 0;
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}
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void serial_putc_dev(unsigned int idx, const char c)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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if (c == '\n')
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serial_putc_dev(idx, '\r');
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/* Wait for last character to go. */
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while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
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;
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out_8(&psc->tfdata_8, c);
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}
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void serial_putc_raw_dev(unsigned int idx, const char c)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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/* Wait for last character to go. */
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while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
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;
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out_8(&psc->tfdata_8, c);
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}
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void serial_puts_dev(unsigned int idx, const char *s)
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{
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while (*s)
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serial_putc_dev(idx, *s++);
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}
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int serial_getc_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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/* Wait for a character to arrive. */
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while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
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;
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return in_8(&psc->rfdata_8);
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}
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int serial_tstc_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
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}
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void serial_setrts_dev(unsigned int idx, int s)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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if (s) {
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/* Assert RTS (become LOW) */
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out_8(&psc->op1, 0x1);
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}
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else {
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/* Negate RTS (become HIGH) */
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out_8(&psc->op0, 0x1);
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}
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}
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int serial_getcts_dev(unsigned int idx)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
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return (in_8(&psc->ip) & 0x1) ? 0 : 1;
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}
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#endif /* CONFIG_PSC_CONSOLE */
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#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
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int serial##port##_init(void) \
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{ \
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return serial_init_dev(port); \
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} \
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int serial##port##_uninit(void) \
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{ \
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return serial_uninit_dev(port); \
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} \
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void serial##port##_setbrg(void) \
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{ \
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serial_setbrg_dev(port); \
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} \
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int serial##port##_getc(void) \
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{ \
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return serial_getc_dev(port); \
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} \
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int serial##port##_tstc(void) \
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{ \
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return serial_tstc_dev(port); \
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} \
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void serial##port##_putc(const char c) \
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{ \
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serial_putc_dev(port, c); \
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} \
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void serial##port##_puts(const char *s) \
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{ \
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serial_puts_dev(port, s); \
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}
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#define INIT_PSC_SERIAL_STRUCTURE(port, __name) { \
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.name = __name, \
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.start = serial##port##_init, \
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.stop = serial##port##_uninit, \
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.setbrg = serial##port##_setbrg, \
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.getc = serial##port##_getc, \
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.tstc = serial##port##_tstc, \
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.putc = serial##port##_putc, \
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.puts = serial##port##_puts, \
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}
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#if defined(CONFIG_SYS_PSC1)
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DECLARE_PSC_SERIAL_FUNCTIONS(1);
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struct serial_device serial1_device =
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INIT_PSC_SERIAL_STRUCTURE(1, "psc1");
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#endif
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#if defined(CONFIG_SYS_PSC3)
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DECLARE_PSC_SERIAL_FUNCTIONS(3);
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struct serial_device serial3_device =
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INIT_PSC_SERIAL_STRUCTURE(3, "psc3");
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#endif
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#if defined(CONFIG_SYS_PSC4)
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DECLARE_PSC_SERIAL_FUNCTIONS(4);
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struct serial_device serial4_device =
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INIT_PSC_SERIAL_STRUCTURE(4, "psc4");
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#endif
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#if defined(CONFIG_SYS_PSC6)
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DECLARE_PSC_SERIAL_FUNCTIONS(6);
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struct serial_device serial6_device =
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INIT_PSC_SERIAL_STRUCTURE(6, "psc6");
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#endif
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__weak struct serial_device *default_serial_console(void)
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{
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#if (CONFIG_PSC_CONSOLE == 3)
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return &serial3_device;
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#elif (CONFIG_PSC_CONSOLE == 6)
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return &serial6_device;
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#else
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#error "invalid CONFIG_PSC_CONSOLE"
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#endif
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}
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void mpc512x_serial_initialize(void)
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{
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#if defined(CONFIG_SYS_PSC1)
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serial_register(&serial1_device);
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#endif
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#if defined(CONFIG_SYS_PSC3)
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serial_register(&serial3_device);
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#endif
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#if defined(CONFIG_SYS_PSC4)
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serial_register(&serial4_device);
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#endif
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#if defined(CONFIG_SYS_PSC6)
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serial_register(&serial6_device);
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#endif
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}
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#include <stdio_dev.h>
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/*
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* Routines for communication with serial devices over PSC
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*/
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/* Bitfield for initialized PSCs */
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static unsigned int initialized;
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struct stdio_dev *open_port(int num, int baudrate)
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{
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struct stdio_dev *port;
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char env_var[16];
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char env_val[10];
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char name[7];
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if (num < 0 || num > 11)
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return NULL;
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sprintf(name, "psc%d", num);
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port = stdio_get_by_name(name);
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if (!port)
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return NULL;
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if (!test_bit(num, &initialized)) {
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sprintf(env_var, "psc%d_baudrate", num);
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sprintf(env_val, "%d", baudrate);
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setenv(env_var, env_val);
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if (port->start(port))
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return NULL;
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set_bit(num, &initialized);
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}
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return port;
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}
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int close_port(int num)
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{
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struct stdio_dev *port;
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int ret;
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char name[7];
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if (num < 0 || num > 11)
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return -1;
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sprintf(name, "psc%d", num);
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port = stdio_get_by_name(name);
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if (!port)
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return -1;
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ret = port->stop(port);
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clear_bit(num, &initialized);
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return ret;
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}
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int write_port(struct stdio_dev *port, char *buf)
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{
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if (!port || !buf)
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return -1;
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port->puts(port, buf);
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return 0;
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}
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int read_port(struct stdio_dev *port, char *buf, int size)
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{
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int cnt = 0;
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if (!port || !buf)
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return -1;
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if (!size)
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return 0;
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while (port->tstc(port)) {
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buf[cnt++] = port->getc(port);
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if (cnt > size)
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break;
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}
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return cnt;
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}
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