upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Dave Gerlach b56b9a0884 ARM: AM43xx: Change DDR3 Reset Value ... The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>		11 years ago
..
Makefile	…
board.c	…
clock.c	…
clock_am33xx.c	…
clock_am43xx.c	ARM: AM43xx: clocks: Enable CPGMAC clock control	11 years ago
clock_ti814x.c	…
clock_ti816x.c	…
config.mk	…
ddr.c	ARM: AM43xx: Write sdram_config to secure_emif_sdram_config	11 years ago
emif4.c	ARM: AM43xx: Change DDR3 Reset Value	11 years ago
mem.c	…
mux.c	…
sys_info.c	…
u-boot-spl.lds	…