upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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199 lines
6.1 KiB
199 lines
6.1 KiB
/*----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of the
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| GNU General Public License version 2, or under the license below.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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| Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: miiphy.h
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| Function: Include file defining PHY registers.
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| Author: Mark Wisner
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+----------------------------------------------------------------------------*/
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#ifndef _miiphy_h_
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#define _miiphy_h_
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#include <net.h>
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int miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value);
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int miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
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unsigned short value);
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int miiphy_info (const char *devname, unsigned char addr, unsigned int *oui,
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unsigned char *model, unsigned char *rev);
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int miiphy_reset (const char *devname, unsigned char addr);
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int miiphy_speed (const char *devname, unsigned char addr);
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int miiphy_duplex (const char *devname, unsigned char addr);
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int miiphy_is_1000base_x (const char *devname, unsigned char addr);
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#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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int miiphy_link (const char *devname, unsigned char addr);
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#endif
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void miiphy_init (void);
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void miiphy_register (const char *devname,
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int (*read) (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value),
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int (*write) (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value));
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int miiphy_set_current_dev (const char *devname);
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const char *miiphy_get_current_dev (void);
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void miiphy_listdev (void);
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#ifdef CONFIG_BITBANGMII
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#define BB_MII_DEVNAME "bb_miiphy"
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struct bb_miiphy_bus {
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char name[NAMESIZE];
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int (*init)(struct bb_miiphy_bus *bus);
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int (*mdio_active)(struct bb_miiphy_bus *bus);
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int (*mdio_tristate)(struct bb_miiphy_bus *bus);
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int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
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int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
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int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
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int (*delay)(struct bb_miiphy_bus *bus);
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#ifdef CONFIG_BITBANGMII_MULTI
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void *priv;
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#endif
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};
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extern struct bb_miiphy_bus bb_miiphy_buses[];
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extern int bb_miiphy_buses_num;
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void bb_miiphy_init (void);
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int bb_miiphy_read (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value);
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int bb_miiphy_write (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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#endif
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/* phy seed setup */
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#define AUTO 99
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#define _1000BASET 1000
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#define _100BASET 100
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#define _10BASET 10
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#define HALF 22
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#define FULL 44
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/* phy register offsets */
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#define PHY_BMCR 0x00
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#define PHY_BMSR 0x01
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#define PHY_PHYIDR1 0x02
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#define PHY_PHYIDR2 0x03
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#define PHY_ANAR 0x04
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_ANNPTR 0x07
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#define PHY_ANLPNP 0x08
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#define PHY_1000BTCR 0x09
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#define PHY_1000BTSR 0x0A
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#define PHY_EXSR 0x0F
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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#define PHY_DCR 0x13
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#define PHY_FCSCR 0x14
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#define PHY_RECR 0x15
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#define PHY_PCSR 0x16
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#define PHY_LBR 0x17
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#define PHY_10BTSCR 0x18
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#define PHY_PHYCTRL 0x19
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/* PHY BMCR */
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOP 0x4000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_AUTON 0x1000
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#define PHY_BMCR_POWD 0x0800
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#define PHY_BMCR_ISO 0x0400
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#define PHY_BMCR_RST_NEG 0x0200
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#define PHY_BMCR_DPLX 0x0100
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#define PHY_BMCR_COL_TST 0x0080
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#define PHY_BMCR_SPEED_MASK 0x2040
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#define PHY_BMCR_1000_MBPS 0x0040
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#define PHY_BMCR_100_MBPS 0x2000
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#define PHY_BMCR_10_MBPS 0x0000
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/* phy BMSR */
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#define PHY_BMSR_100T4 0x8000
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#define PHY_BMSR_100TXF 0x4000
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#define PHY_BMSR_100TXH 0x2000
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#define PHY_BMSR_10TF 0x1000
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#define PHY_BMSR_10TH 0x0800
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#define PHY_BMSR_EXT_STAT 0x0100
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#define PHY_BMSR_PRE_SUP 0x0040
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#define PHY_BMSR_AUTN_COMP 0x0020
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#define PHY_BMSR_RF 0x0010
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#define PHY_BMSR_AUTN_ABLE 0x0008
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#define PHY_BMSR_LS 0x0004
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#define PHY_BMSR_JD 0x0002
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#define PHY_BMSR_EXT 0x0001
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/*phy ANLPAR */
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#define PHY_ANLPAR_NP 0x8000
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#define PHY_ANLPAR_ACK 0x4000
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#define PHY_ANLPAR_RF 0x2000
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#define PHY_ANLPAR_ASYMP 0x0800
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#define PHY_ANLPAR_PAUSE 0x0400
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#define PHY_ANLPAR_T4 0x0200
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#define PHY_ANLPAR_TXFD 0x0100
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_10FD 0x0040
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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/* phy ANLPAR 1000BASE-X */
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#define PHY_X_ANLPAR_NP 0x8000
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#define PHY_X_ANLPAR_ACK 0x4000
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#define PHY_X_ANLPAR_RF_MASK 0x3000
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#define PHY_X_ANLPAR_PAUSE_MASK 0x0180
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#define PHY_X_ANLPAR_HD 0x0040
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#define PHY_X_ANLPAR_FD 0x0020
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#define PHY_ANLPAR_PSB_MASK 0x001f
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#define PHY_ANLPAR_PSB_802_3 0x0001
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#define PHY_ANLPAR_PSB_802_9 0x0002
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/* phy 1000BTCR */
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#define PHY_1000BTCR_1000FD 0x0200
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#define PHY_1000BTCR_1000HD 0x0100
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/* phy 1000BTSR */
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#define PHY_1000BTSR_MSCF 0x8000
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#define PHY_1000BTSR_MSCR 0x4000
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#define PHY_1000BTSR_LRS 0x2000
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#define PHY_1000BTSR_RRS 0x1000
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#define PHY_1000BTSR_1000FD 0x0800
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#define PHY_1000BTSR_1000HD 0x0400
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/* phy EXSR */
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#define PHY_EXSR_1000XF 0x8000
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#define PHY_EXSR_1000XH 0x4000
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#define PHY_EXSR_1000TF 0x2000
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#define PHY_EXSR_1000TH 0x1000
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#endif
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