upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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424 lines
15 KiB
424 lines
15 KiB
/*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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int board_early_init_f(void)
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{
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register uint reg;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(ebccfga, xbcfg);
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
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mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
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mtebc(pb1ap, 0x00000000);
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mtebc(pb1cr, 0x00000000);
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mtebc(pb2ap, 0x04814500);
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/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
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mtebc(pb3ap, 0x00000000);
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mtebc(pb3cr, 0x00000000);
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mtebc(pb4ap, 0x00000000);
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mtebc(pb4cr, 0x00000000);
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/*CPLD cs */
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/*setup Address lines for flash sizes larger than 16Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
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/*setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
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/*UART1 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
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/*setup USB 2.0 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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/*--------------------------------------------------------------------
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* Setup other serial configuration
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*-------------------------------------------------------------------*/
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
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/*clear tmrclk divisor */
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*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
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/*enable ethernet */
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*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
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/*enable usb 1.1 fs device and remove usb 2.0 reset */
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*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
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/*get rid of flash write protect */
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
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return 0;
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}
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int checkboard(void)
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{
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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printf("Board: AMCC YOSEMITE\n");
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printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
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printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
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printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
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printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
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printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
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return (0);
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}
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/*************************************************************************
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* sdram_init -- doesn't use serial presence detect.
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*
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* Assumes: 256 MB, ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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void sdram_init(void)
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{
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register uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(mem_clktr, 0x40000000); /* ?? */
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mtsdram(mem_wddctr, 0x40000000); /* ?? */
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/*clear this first, if the DDR is enabled by a debugger
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then you can not make changes. */
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mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
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mtsdram(mem_tr0, 0x410a4012); /* ?? */
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mtsdram(mem_tr1, 0x8080080b); /* ?? */
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mtsdram(mem_rtr, 0x04080000); /* ?? */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(mem_cfg0, 0x84000000); /* Enable */
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for (;;) {
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mfsdram(mem_mcsts, reg);
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if (reg & 0x80000000)
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break;
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}
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}
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/*************************************************************************
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* long int initdram
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*
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************************************************************************/
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long int initdram(int board)
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{
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sdram_init();
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return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
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}
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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unsigned long *mem = (unsigned long *)0;
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const unsigned long kend = (1024 / sizeof(unsigned long));
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unsigned long k, n;
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mtmsr(0);
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for (k = 0; k < CFG_KBYTES_SDRAM;
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++k, mem += (1024 / sizeof(unsigned long))) {
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if ((k & 1023) == 0) {
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printf("%3d MB\r", k / 1024);
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}
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memset(mem, 0xaaaaaaaa, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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memset(mem, 0x55555555, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0x55555555) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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}
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printf("SDRAM test passes\n");
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return 0;
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}
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#endif
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long strap;
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unsigned long addr;
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/*--------------------------------------------------------------------------+
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* Bamboo is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
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printf("PCI: SDR0_STRP1[PAE] not set.\n");
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printf("PCI: Configuration aborted.\n");
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return 0;
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}
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/*-------------------------------------------------------------------------+
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| Set priority for all PLB3 devices to 0.
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| Set PLB3 arbiter to fair mode.
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+-------------------------------------------------------------------------*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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mtdcr(plb3_acr, addr | 0x80000000);
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/*-------------------------------------------------------------------------+
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| Set priority for all PLB4 devices to 0.
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+-------------------------------------------------------------------------*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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mtdcr(plb4_acr, addr);
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/*-------------------------------------------------------------------------+
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| Set Nebula PLB4 arbiter to fair mode.
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+-------------------------------------------------------------------------*/
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/* Segment0 */
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
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mtdcr(plb0_acr, addr);
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/* Segment1 */
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addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
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addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
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addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
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addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
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mtdcr(plb1_acr, addr);
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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* Set up Direct MMIO registers
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*--------------------------------------------------------------------------*/
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/*--------------------------------------------------------------------------+
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| PowerPC440 EP PCI Master configuration.
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| Map one 1Gig range of PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
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out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
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out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
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out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
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out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
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out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
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out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
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out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
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/*--------------------------------------------------------------------------+
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* Set up Configuration registers
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*--------------------------------------------------------------------------*/
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/* Program the board's subsystem id/vendor id */
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pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
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CFG_PCI_SUBSYS_VENDORID);
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pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
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/* Configure command register as bus master */
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pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* 240nS PCI clock */
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pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
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/* No error reporting */
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pci_write_config_word(0, PCI_ERREN, 0);
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pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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unsigned short temp_short;
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/*--------------------------------------------------------------------------+
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| Write the PowerPC440 EP PCI Configuration regs.
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| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
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| Enable PowerPC440 EP to act as a PCI memory target (PTM).
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+--------------------------------------------------------------------------*/
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pci_read_config_word(0, PCI_COMMAND, &temp_short);
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pci_write_config_word(0, PCI_COMMAND,
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temp_short | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* Bamboo is always configured as host. */
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return (1);
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* hw_watchdog_reset
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*
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* This routine is called to reset (keep alive) the watchdog timer
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*
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************************************************************************/
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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}
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#endif
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