upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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677 lines
20 KiB
677 lines
20 KiB
/*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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* (C) Copyright 2007 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Derived from the MPC83xx header.
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*/
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#ifndef __MPC512X_H__
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#define __MPC512X_H__
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#include <config.h>
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#if defined(CONFIG_E300)
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#include <asm/e300.h>
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#endif
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/* System reset offset (PowerPC standard)
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*/
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#define EXC_OFF_SYS_RESET 0x0100
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#define _START_OFFSET EXC_OFF_SYS_RESET
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/* IMMRBAR - Internal Memory Register Base Address
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*/
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#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
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#define IMMRBAR 0x0000 /* Register offset to immr */
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#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
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#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
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/* LAWBAR - Local Access Window Base Address Register
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*/
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#define LPBAW 0x0020 /* Register offset to immr */
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#define LPCS0AW 0x0024
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#define LPCS1AW 0x0028
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#define LPCS2AW 0x002C
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#define LPCS3AW 0x0030
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#define LPCS4AW 0x0034
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#define LPCS5AW 0x0038
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#define LPCS6AW 0x003C
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#define LPCA7AW 0x0040
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#define SRAMBAR 0x00C4
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#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
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#define LPC_OFFSET 0x10000
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#define CS0_CONFIG 0x00000
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#define CS1_CONFIG 0x00004
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#define CS2_CONFIG 0x00008
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#define CS3_CONFIG 0x0000C
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#define CS4_CONFIG 0x00010
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#define CS5_CONFIG 0x00014
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#define CS6_CONFIG 0x00018
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#define CS7_CONFIG 0x0001C
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#define CS_ALE_TIMING_CONFIG 0x00034
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#define CS_CTRL 0x00020
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#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
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#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
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/* SPRIDR - System Part and Revision ID Register
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*/
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#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
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#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
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#define SPR_5121E 0x80180000
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/* SPCR - System Priority Configuration Register
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*/
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#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
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#define SPCR_PCIHPE_SHIFT (31-3)
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#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
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#define SPCR_PCIPR_SHIFT (31-7)
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#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
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#define SPCR_TBEN_SHIFT (31-9)
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#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
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#define SPCR_COREPR_SHIFT (31-11)
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/* SWCRR - System Watchdog Control Register
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*/
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#define SWCRR 0x0904 /* Register offset to immr */
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#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
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#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
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#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
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#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
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#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
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/* SWCNR - System Watchdog Counter Register
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*/
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#define SWCNR 0x0908 /* Register offset to immr */
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#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
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#define SWCNR_RES ~(SWCNR_SWCN)
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/* SWSRR - System Watchdog Service Register
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*/
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#define SWSRR 0x090E /* Register offset to immr */
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/* ACR - Arbiter Configuration Register
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*/
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#define ACR_COREDIS 0x10000000 /* Core disable */
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#define ACR_COREDIS_SHIFT (31-7)
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#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
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#define ACR_PIPE_DEP_SHIFT (31-15)
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#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
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#define ACR_PCI_RPTCNT_SHIFT (31-19)
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#define ACR_RPTCNT 0x00000700 /* Repeat count */
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#define ACR_RPTCNT_SHIFT (31-23)
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#define ACR_APARK 0x00000030 /* Address parking */
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#define ACR_APARK_SHIFT (31-27)
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#define ACR_PARKM 0x0000000F /* Parking master */
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#define ACR_PARKM_SHIFT (31-31)
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/* ATR - Arbiter Timers Register
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*/
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#define ATR_DTO 0x00FF0000 /* Data time out */
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#define ATR_ATO 0x000000FF /* Address time out */
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/* AER - Arbiter Event Register
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*/
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#define AER_ETEA 0x00000020 /* Transfer error */
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#define AER_RES 0x00000010 /* Reserved transfer type */
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#define AER_ECW 0x00000008 /* External control word transfer type */
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#define AER_AO 0x00000004 /* Address Only transfer type */
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#define AER_DTO 0x00000002 /* Data time out */
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#define AER_ATO 0x00000001 /* Address time out */
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/* AEATR - Arbiter Event Address Register
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*/
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#define AEATR_EVENT 0x07000000 /* Event type */
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#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
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#define AEATR_TBST 0x00000800 /* Transfer burst */
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#define AEATR_TSIZE 0x00000700 /* Transfer Size */
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#define AEATR_TTYPE 0x0000001F /* Transfer Type */
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/* RSR - Reset Status Register
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*/
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#define RSR_SWSR 0x00002000 /* software soft reset */
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#define RSR_SWSR_SHIFT 13
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#define RSR_SWHR 0x00001000 /* software hard reset */
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#define RSR_SWHR_SHIFT 12
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#define RSR_JHRS 0x00000200 /* jtag hreset */
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#define RSR_JHRS_SHIFT 9
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#define RSR_JSRS 0x00000100 /* jtag sreset status */
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#define RSR_JSRS_SHIFT 8
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#define RSR_CSHR 0x00000010 /* checkstop reset status */
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#define RSR_CSHR_SHIFT 4
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#define RSR_SWRS 0x00000008 /* software watchdog reset status */
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#define RSR_SWRS_SHIFT 3
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#define RSR_BMRS 0x00000004 /* bus monitop reset status */
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#define RSR_BMRS_SHIFT 2
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#define RSR_SRS 0x00000002 /* soft reset status */
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#define RSR_SRS_SHIFT 1
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#define RSR_HRS 0x00000001 /* hard reset status */
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#define RSR_HRS_SHIFT 0
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#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\
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RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
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RSR_BMRS | RSR_SRS | RSR_HRS)
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/* RMR - Reset Mode Register
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*/
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#define RMR_CSRE 0x00000001 /* checkstop reset enable */
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#define RMR_CSRE_SHIFT 0
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#define RMR_RES ~(RMR_CSRE)
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/* RCR - Reset Control Register
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*/
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#define RCR_SWHR 0x00000002 /* software hard reset */
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#define RCR_SWSR 0x00000001 /* software soft reset */
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#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
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/* RCER - Reset Control Enable Register
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*/
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#define RCER_CRE 0x00000001 /* software hard reset */
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#define RCER_RES ~(RCER_CRE)
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/* SPMR - System PLL Mode Register
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*/
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#define SPMR_SPMF 0x0F000000
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#define SPMR_SPMF_SHIFT 24
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#define SPMR_CPMF 0x000F0000
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#define SPMR_CPMF_SHIFT 16
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/* SCFR1 System Clock Frequency Register 1
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*/
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#define SCFR1_IPS_DIV 0x3
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#define SCFR1_IPS_DIV_MASK 0x03800000
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#define SCFR1_IPS_DIV_SHIFT 23
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#define SCFR1_PCI_DIV 0x6
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#define SCFR1_PCI_DIV_MASK 0x00700000
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#define SCFR1_PCI_DIV_SHIFT 20
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/* SCFR2 System Clock Frequency Register 2
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*/
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#define SCFR2_SYS_DIV 0xFC000000
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#define SCFR2_SYS_DIV_SHIFT 26
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/* SCCR - System Clock Control Registers
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*/
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/* System Clock Control Register 1 commands */
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#define CLOCK_SCCR1_CFG_EN 0x80000000
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#define CLOCK_SCCR1_LPC_EN 0x40000000
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#define CLOCK_SCCR1_NFC_EN 0x20000000
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#define CLOCK_SCCR1_PATA_EN 0x10000000
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#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn))
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#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000
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#define CLOCK_SCCR1_SATA_EN 0x00004000
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#define CLOCK_SCCR1_FEC_EN 0x00002000
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#define CLOCK_SCCR1_TPR_EN 0x00001000
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#define CLOCK_SCCR1_PCI_EN 0x00000800
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#define CLOCK_SCCR1_DDR_EN 0x00000400
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/* System Clock Control Register 2 commands */
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#define CLOCK_SCCR2_DIU_EN 0x80000000
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#define CLOCK_SCCR2_AXE_EN 0x40000000
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#define CLOCK_SCCR2_MEM_EN 0x20000000
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#define CLOCK_SCCR2_USB2_EN 0x10000000
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#define CLOCK_SCCR2_USB1_EN 0x08000000
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#define CLOCK_SCCR2_I2C_EN 0x04000000
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#define CLOCK_SCCR2_BDLC_EN 0x02000000
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#define CLOCK_SCCR2_SDHC_EN 0x01000000
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#define CLOCK_SCCR2_SPDIF_EN 0x00800000
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#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000
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#define CLOCK_SCCR2_MBX_EN 0x00200000
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#define CLOCK_SCCR2_MBX_3D_EN 0x00100000
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#define CLOCK_SCCR2_IIM_EN 0x00080000
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/* PSC FIFO Command values */
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#define PSC_FIFO_RESET_SLICE 0x80
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#define PSC_FIFO_ENABLE_SLICE 0x01
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/* PSC FIFO Controller Command values */
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#define FIFOC_ENABLE_CLOCK_GATE 0x01
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#define FIFOC_DISABLE_CLOCK_GATE 0x00
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/* PSC FIFO status */
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#define PSC_FIFO_EMPTY 0x01
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/* PSC Command values */
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#define PSC_RX_ENABLE 0x01
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#define PSC_RX_DISABLE 0x02
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#define PSC_TX_ENABLE 0x04
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#define PSC_TX_DISABLE 0x08
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#define PSC_SEL_MODE_REG_1 0x10
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#define PSC_RST_RX 0x20
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#define PSC_RST_TX 0x30
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#define PSC_RST_ERR_STAT 0x40
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#define PSC_RST_BRK_CHG_INT 0x50
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#define PSC_START_BRK 0x60
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#define PSC_STOP_BRK 0x70
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/* PSC status register bits */
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#define PSC_SR_CDE 0x0080
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#define PSC_SR_TXEMP 0x0800
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#define PSC_SR_OE 0x1000
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#define PSC_SR_PE 0x2000
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#define PSC_SR_FE 0x4000
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#define PSC_SR_RB 0x8000
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/* PSC mode fields */
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#define PSC_MODE_5_BITS 0x00
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#define PSC_MODE_6_BITS 0x01
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#define PSC_MODE_7_BITS 0x02
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#define PSC_MODE_8_BITS 0x03
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#define PSC_MODE_PAREVEN 0x00
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#define PSC_MODE_PARODD 0x04
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#define PSC_MODE_PARFORCE 0x08
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#define PSC_MODE_PARNONE 0x10
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#define PSC_MODE_ENTIMEOUT 0x20
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#define PSC_MODE_RXRTS 0x80
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#define PSC_MODE_1_STOPBIT 0x07
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/*
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* Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
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*
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* NOTE: individual PSC units are free to use whatever area (and size) of the
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* FIFOC internal memory, so make sure memory areas for FIFO slices used by
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* different PSCs do not overlap!
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*
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* Overall size of FIFOC memory is not documented in the MPC5121e RM, but
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* tests indicate that it is 1024 words total.
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*/
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#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */
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#define FIFOC_PSC0_TX_ADDR 0x0
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#define FIFOC_PSC0_RX_SIZE 0x0
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#define FIFOC_PSC0_RX_ADDR 0x0
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#define FIFOC_PSC1_TX_SIZE 0x0
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#define FIFOC_PSC1_TX_ADDR 0x0
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#define FIFOC_PSC1_RX_SIZE 0x0
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#define FIFOC_PSC1_RX_ADDR 0x0
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#define FIFOC_PSC2_TX_SIZE 0x0
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#define FIFOC_PSC2_TX_ADDR 0x0
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#define FIFOC_PSC2_RX_SIZE 0x0
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#define FIFOC_PSC2_RX_ADDR 0x0
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#define FIFOC_PSC3_TX_SIZE 0x04
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#define FIFOC_PSC3_TX_ADDR 0x0
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#define FIFOC_PSC3_RX_SIZE 0x04
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#define FIFOC_PSC3_RX_ADDR 0x10
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#define FIFOC_PSC4_TX_SIZE 0x0
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#define FIFOC_PSC4_TX_ADDR 0x0
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#define FIFOC_PSC4_RX_SIZE 0x0
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#define FIFOC_PSC4_RX_ADDR 0x0
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#define FIFOC_PSC5_TX_SIZE 0x0
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#define FIFOC_PSC5_TX_ADDR 0x0
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#define FIFOC_PSC5_RX_SIZE 0x0
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#define FIFOC_PSC5_RX_ADDR 0x0
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#define FIFOC_PSC6_TX_SIZE 0x0
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#define FIFOC_PSC6_TX_ADDR 0x0
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#define FIFOC_PSC6_RX_SIZE 0x0
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#define FIFOC_PSC6_RX_ADDR 0x0
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#define FIFOC_PSC7_TX_SIZE 0x0
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#define FIFOC_PSC7_TX_ADDR 0x0
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#define FIFOC_PSC7_RX_SIZE 0x0
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#define FIFOC_PSC7_RX_ADDR 0x0
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#define FIFOC_PSC8_TX_SIZE 0x0
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#define FIFOC_PSC8_TX_ADDR 0x0
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#define FIFOC_PSC8_RX_SIZE 0x0
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#define FIFOC_PSC8_RX_ADDR 0x0
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#define FIFOC_PSC9_TX_SIZE 0x0
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#define FIFOC_PSC9_TX_ADDR 0x0
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#define FIFOC_PSC9_RX_SIZE 0x0
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#define FIFOC_PSC9_RX_ADDR 0x0
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#define FIFOC_PSC10_TX_SIZE 0x0
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#define FIFOC_PSC10_TX_ADDR 0x0
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#define FIFOC_PSC10_RX_SIZE 0x0
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#define FIFOC_PSC10_RX_ADDR 0x0
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#define FIFOC_PSC11_TX_SIZE 0x0
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#define FIFOC_PSC11_TX_ADDR 0x0
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#define FIFOC_PSC11_RX_SIZE 0x0
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#define FIFOC_PSC11_RX_ADDR 0x0
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/* IO Control Register
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*/
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#define IOCTL_MEM 0x000
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#define IOCTL_GP 0x004
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#define IOCTL_LPC_CLK 0x008
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#define IOCTL_LPC_OE 0x00C
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#define IOCTL_LPC_RWB 0x010
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#define IOCTL_LPC_ACK 0x014
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#define IOCTL_LPC_CS0 0x018
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#define IOCTL_NFC_CE0 0x01C
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#define IOCTL_LPC_CS1 0x020
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#define IOCTL_LPC_CS2 0x024
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#define IOCTL_LPC_AX03 0x028
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#define IOCTL_EMB_AX02 0x02C
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#define IOCTL_EMB_AX01 0x030
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#define IOCTL_EMB_AX00 0x034
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#define IOCTL_EMB_AD31 0x038
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#define IOCTL_EMB_AD30 0x03C
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#define IOCTL_EMB_AD29 0x040
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#define IOCTL_EMB_AD28 0x044
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#define IOCTL_EMB_AD27 0x048
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#define IOCTL_EMB_AD26 0x04C
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#define IOCTL_EMB_AD25 0x050
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#define IOCTL_EMB_AD24 0x054
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#define IOCTL_EMB_AD23 0x058
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#define IOCTL_EMB_AD22 0x05C
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#define IOCTL_EMB_AD21 0x060
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#define IOCTL_EMB_AD20 0x064
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#define IOCTL_EMB_AD19 0x068
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#define IOCTL_EMB_AD18 0x06C
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#define IOCTL_EMB_AD17 0x070
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#define IOCTL_EMB_AD16 0x074
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#define IOCTL_EMB_AD15 0x078
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#define IOCTL_EMB_AD14 0x07C
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#define IOCTL_EMB_AD13 0x080
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#define IOCTL_EMB_AD12 0x084
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#define IOCTL_EMB_AD11 0x088
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#define IOCTL_EMB_AD10 0x08C
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#define IOCTL_EMB_AD09 0x090
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#define IOCTL_EMB_AD08 0x094
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#define IOCTL_EMB_AD07 0x098
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#define IOCTL_EMB_AD06 0x09C
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#define IOCTL_EMB_AD05 0x0A0
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#define IOCTL_EMB_AD04 0x0A4
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#define IOCTL_EMB_AD03 0x0A8
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#define IOCTL_EMB_AD02 0x0AC
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#define IOCTL_EMB_AD01 0x0B0
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#define IOCTL_EMB_AD00 0x0B4
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#define IOCTL_PATA_CE1 0x0B8
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#define IOCTL_PATA_CE2 0x0BC
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#define IOCTL_PATA_ISOLATE 0x0C0
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#define IOCTL_PATA_IOR 0x0C4
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#define IOCTL_PATA_IOW 0x0C8
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#define IOCTL_PATA_IOCHRDY 0x0CC
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#define IOCTL_PATA_INTRQ 0x0D0
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#define IOCTL_PATA_DRQ 0x0D4
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#define IOCTL_PATA_DACK 0x0D8
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#define IOCTL_NFC_WP 0x0DC
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#define IOCTL_NFC_RB 0x0E0
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#define IOCTL_NFC_ALE 0x0E4
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#define IOCTL_NFC_CLE 0x0E8
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#define IOCTL_NFC_WE 0x0EC
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#define IOCTL_NFC_RE 0x0F0
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#define IOCTL_PCI_AD31 0x0F4
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#define IOCTL_PCI_AD30 0x0F8
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#define IOCTL_PCI_AD29 0x0FC
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#define IOCTL_PCI_AD28 0x100
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#define IOCTL_PCI_AD27 0x104
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#define IOCTL_PCI_AD26 0x108
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#define IOCTL_PCI_AD25 0x10C
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#define IOCTL_PCI_AD24 0x110
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#define IOCTL_PCI_AD23 0x114
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#define IOCTL_PCI_AD22 0x118
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#define IOCTL_PCI_AD21 0x11C
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#define IOCTL_PCI_AD20 0x120
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#define IOCTL_PCI_AD19 0x124
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#define IOCTL_PCI_AD18 0x128
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#define IOCTL_PCI_AD17 0x12C
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#define IOCTL_PCI_AD16 0x130
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#define IOCTL_PCI_AD15 0x134
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#define IOCTL_PCI_AD14 0x138
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#define IOCTL_PCI_AD13 0x13C
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#define IOCTL_PCI_AD12 0x140
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#define IOCTL_PCI_AD11 0x144
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#define IOCTL_PCI_AD10 0x148
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#define IOCTL_PCI_AD09 0x14C
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#define IOCTL_PCI_AD08 0x150
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#define IOCTL_PCI_AD07 0x154
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#define IOCTL_PCI_AD06 0x158
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#define IOCTL_PCI_AD05 0x15C
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#define IOCTL_PCI_AD04 0x160
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#define IOCTL_PCI_AD03 0x164
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#define IOCTL_PCI_AD02 0x168
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#define IOCTL_PCI_AD01 0x16C
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#define IOCTL_PCI_AD00 0x170
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#define IOCTL_PCI_CBE0 0x174
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#define IOCTL_PCI_CBE1 0x178
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#define IOCTL_PCI_CBE2 0x17C
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#define IOCTL_PCI_CBE3 0x180
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#define IOCTL_PCI_GNT2 0x184
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#define IOCTL_PCI_REQ2 0x188
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#define IOCTL_PCI_GNT1 0x18C
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#define IOCTL_PCI_REQ1 0x190
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#define IOCTL_PCI_GNT0 0x194
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#define IOCTL_PCI_REQ0 0x198
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#define IOCTL_PCI_INTA 0x19C
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#define IOCTL_PCI_CLK 0x1A0
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#define IOCTL_PCI_RST_OUT 0x1A4
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#define IOCTL_PCI_FRAME 0x1A8
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#define IOCTL_PCI_IDSEL 0x1AC
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#define IOCTL_PCI_DEVSEL 0x1B0
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#define IOCTL_PCI_IRDY 0x1B4
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#define IOCTL_PCI_TRDY 0x1B8
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#define IOCTL_PCI_STOP 0x1BC
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#define IOCTL_PCI_PAR 0x1C0
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#define IOCTL_PCI_PERR 0x1C4
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#define IOCTL_PCI_SERR 0x1C8
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#define IOCTL_SPDIF_TXCLK 0x1CC
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#define IOCTL_SPDIF_TX 0x1D0
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#define IOCTL_SPDIF_RX 0x1D4
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#define IOCTL_I2C0_SCL 0x1D8
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#define IOCTL_I2C0_SDA 0x1DC
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#define IOCTL_I2C1_SCL 0x1E0
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#define IOCTL_I2C1_SDA 0x1E4
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#define IOCTL_I2C2_SCL 0x1E8
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#define IOCTL_I2C2_SDA 0x1EC
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#define IOCTL_IRQ0 0x1F0
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#define IOCTL_IRQ1 0x1F4
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#define IOCTL_CAN1_TX 0x1F8
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#define IOCTL_CAN2_TX 0x1FC
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#define IOCTL_J1850_TX 0x200
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#define IOCTL_J1850_RX 0x204
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#define IOCTL_PSC_MCLK_IN 0x208
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#define IOCTL_PSC0_0 0x20C
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#define IOCTL_PSC0_1 0x210
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#define IOCTL_PSC0_2 0x214
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#define IOCTL_PSC0_3 0x218
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#define IOCTL_PSC0_4 0x21C
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#define IOCTL_PSC1_0 0x220
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#define IOCTL_PSC1_1 0x224
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#define IOCTL_PSC1_2 0x228
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#define IOCTL_PSC1_3 0x22C
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#define IOCTL_PSC1_4 0x230
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#define IOCTL_PSC2_0 0x234
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#define IOCTL_PSC2_1 0x238
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#define IOCTL_PSC2_2 0x23C
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#define IOCTL_PSC2_3 0x240
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#define IOCTL_PSC2_4 0x244
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#define IOCTL_PSC3_0 0x248
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#define IOCTL_PSC3_1 0x24C
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#define IOCTL_PSC3_2 0x250
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#define IOCTL_PSC3_3 0x254
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#define IOCTL_PSC3_4 0x258
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#define IOCTL_PSC4_0 0x25C
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#define IOCTL_PSC4_1 0x260
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#define IOCTL_PSC4_2 0x264
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#define IOCTL_PSC4_3 0x268
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#define IOCTL_PSC4_4 0x26C
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#define IOCTL_PSC5_0 0x270
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#define IOCTL_PSC5_1 0x274
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#define IOCTL_PSC5_2 0x278
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#define IOCTL_PSC5_3 0x27C
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#define IOCTL_PSC5_4 0x280
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#define IOCTL_PSC6_0 0x284
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#define IOCTL_PSC6_1 0x288
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#define IOCTL_PSC6_2 0x28C
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#define IOCTL_PSC6_3 0x290
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#define IOCTL_PSC6_4 0x294
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#define IOCTL_PSC7_0 0x298
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#define IOCTL_PSC7_1 0x29C
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#define IOCTL_PSC7_2 0x2A0
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#define IOCTL_PSC7_3 0x2A4
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#define IOCTL_PSC7_4 0x2A8
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#define IOCTL_PSC8_0 0x2AC
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#define IOCTL_PSC8_1 0x2B0
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#define IOCTL_PSC8_2 0x2B4
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#define IOCTL_PSC8_3 0x2B8
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#define IOCTL_PSC8_4 0x2BC
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#define IOCTL_PSC9_0 0x2C0
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#define IOCTL_PSC9_1 0x2C4
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#define IOCTL_PSC9_2 0x2C8
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#define IOCTL_PSC9_3 0x2CC
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#define IOCTL_PSC9_4 0x2D0
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#define IOCTL_PSC10_0 0x2D4
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#define IOCTL_PSC10_1 0x2D8
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#define IOCTL_PSC10_2 0x2DC
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#define IOCTL_PSC10_3 0x2E0
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#define IOCTL_PSC10_4 0x2E4
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#define IOCTL_PSC11_0 0x2E8
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#define IOCTL_PSC11_1 0x2EC
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#define IOCTL_PSC11_2 0x2F0
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#define IOCTL_PSC11_3 0x2F4
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#define IOCTL_PSC11_4 0x2F8
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#define IOCTL_HRESET 0x2FC
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#define IOCTL_SRESET 0x300
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#define IOCTL_CKSTP_OUT 0x304
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#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
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#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
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#define IOCTL_USB2_PHY_DRVV_BUS 0x310
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#ifndef __ASSEMBLY__
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/* IO pin fields */
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#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
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#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
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#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
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#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
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#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
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#define IO_PIN_DS(v) ((v)) /* slew rate */
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typedef struct iopin_t {
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int p_offset; /* offset from IOCTL_MEM_OFFSET */
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int nr_pins; /* number of pins to set this way */
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int bit_or; /* or in the value instead of overwrite */
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u_long val; /* value to write or or */
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}iopin_t;
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void iopin_initialize(iopin_t *,int);
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#endif
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/* Indexes in regs array */
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/* Set for DDR */
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#define IOCTRL_MUX_DDR 0x00000036
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/* Register Offset Base */
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#define MPC512X_FEC (CFG_IMMR + 0x02800)
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/* Number of I2C buses */
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#define I2C_BUS_CNT 3
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/* I2Cn control register bits */
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#define I2C_EN 0x80
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#define I2C_IEN 0x40
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#define I2C_STA 0x20
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#define I2C_TX 0x10
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#define I2C_TXAK 0x08
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#define I2C_RSTA 0x04
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#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
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/* I2Cn status register bits */
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#define I2C_CF 0x80
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#define I2C_AAS 0x40
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#define I2C_BB 0x20
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#define I2C_AL 0x10
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#define I2C_SRW 0x04
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#define I2C_IF 0x02
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#define I2C_RXAK 0x01
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/* POTAR - PCI Outbound Translation Address Register
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*/
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#define POTAR_TA_MASK 0x000fffff
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/* POBAR - PCI Outbound Base Address Register
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*/
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#define POBAR_BA_MASK 0x000fffff
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/* POCMR - PCI Outbound Comparision Mask Register
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*/
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#define POCMR_EN 0x80000000
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#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
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#define POCMR_PRE 0x20000000 /* prefetch enable */
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#define POCMR_SBS 0x00100000 /* special byte swap enable */
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#define POCMR_CM_MASK 0x000fffff
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#define POCMR_CM_4G 0x00000000
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#define POCMR_CM_2G 0x00080000
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#define POCMR_CM_1G 0x000C0000
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#define POCMR_CM_512M 0x000E0000
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#define POCMR_CM_256M 0x000F0000
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#define POCMR_CM_128M 0x000F8000
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#define POCMR_CM_64M 0x000FC000
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#define POCMR_CM_32M 0x000FE000
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#define POCMR_CM_16M 0x000FF000
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#define POCMR_CM_8M 0x000FF800
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#define POCMR_CM_4M 0x000FFC00
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#define POCMR_CM_2M 0x000FFE00
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#define POCMR_CM_1M 0x000FFF00
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#define POCMR_CM_512K 0x000FFF80
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#define POCMR_CM_256K 0x000FFFC0
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#define POCMR_CM_128K 0x000FFFE0
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#define POCMR_CM_64K 0x000FFFF0
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#define POCMR_CM_32K 0x000FFFF8
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#define POCMR_CM_16K 0x000FFFFC
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#define POCMR_CM_8K 0x000FFFFE
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#define POCMR_CM_4K 0x000FFFFF
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/* PITAR - PCI Inbound Translation Address Register
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*/
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#define PITAR_TA_MASK 0x000fffff
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/* PIBAR - PCI Inbound Base/Extended Address Register
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*/
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#define PIBAR_MASK 0xffffffff
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#define PIEBAR_EBA_MASK 0x000fffff
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/* PIWAR - PCI Inbound Windows Attributes Register
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*/
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#define PIWAR_EN 0x80000000
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#define PIWAR_SBS 0x40000000
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#define PIWAR_PF 0x20000000
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#define PIWAR_RTT_MASK 0x000f0000
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#define PIWAR_RTT_NO_SNOOP 0x00040000
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#define PIWAR_RTT_SNOOP 0x00050000
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#define PIWAR_WTT_MASK 0x0000f000
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#define PIWAR_WTT_NO_SNOOP 0x00004000
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#define PIWAR_WTT_SNOOP 0x00005000
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#define PIWAR_IWS_MASK 0x0000003F
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#define PIWAR_IWS_4K 0x0000000B
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#define PIWAR_IWS_8K 0x0000000C
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#define PIWAR_IWS_16K 0x0000000D
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#define PIWAR_IWS_32K 0x0000000E
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#define PIWAR_IWS_64K 0x0000000F
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#define PIWAR_IWS_128K 0x00000010
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#define PIWAR_IWS_256K 0x00000011
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#define PIWAR_IWS_512K 0x00000012
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#define PIWAR_IWS_1M 0x00000013
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#define PIWAR_IWS_2M 0x00000014
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#define PIWAR_IWS_4M 0x00000015
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#define PIWAR_IWS_8M 0x00000016
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#define PIWAR_IWS_16M 0x00000017
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#define PIWAR_IWS_32M 0x00000018
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#define PIWAR_IWS_64M 0x00000019
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#define PIWAR_IWS_128M 0x0000001A
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#define PIWAR_IWS_256M 0x0000001B
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#define PIWAR_IWS_512M 0x0000001C
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#define PIWAR_IWS_1G 0x0000001D
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#define PIWAR_IWS_2G 0x0000001E
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#endif /* __MPC512X_H__ */
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