upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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114 lines
5.7 KiB
114 lines
5.7 KiB
/* ---------------------------------------------------------------------------- */
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/* ATMEL Microcontroller Software Support - ROUSSET - */
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/* ---------------------------------------------------------------------------- */
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/* The software is delivered "AS IS" without warranty or condition of any */
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/* kind, either express, implied or statutory. This includes without */
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/* limitation any warranty or condition with respect to merchantability or */
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/* fitness for any particular purpose, or against the infringements of */
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/* intellectual property rights of others. */
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/* ---------------------------------------------------------------------------- */
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/* File Name : at91rm9200_i2c.h */
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/* Object : AT91RM9200 / TWI definitions */
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/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */
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/* */
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/* ---------------------------------------------------------------------------- */
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#ifndef AT91RM9200_TWI_H
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#define AT91RM9200_TWI_H
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/* ******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Two-wire Interface */
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/* ******************************************************************************/
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#ifndef __ASSEMBLY__
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typedef struct _AT91S_TWI {
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AT91_REG TWI_CR; /* Control Register */
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AT91_REG TWI_MMR; /* Master Mode Register */
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AT91_REG TWI_SMR; /* Slave Mode Register */
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AT91_REG TWI_IADR; /* Internal Address Register */
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AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
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AT91_REG Reserved0[3];
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AT91_REG TWI_SR; /* Status Register */
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AT91_REG TWI_IER; /* Interrupt Enable Register */
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AT91_REG TWI_IDR; /* Interrupt Disable Register */
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AT91_REG TWI_IMR; /* Interrupt Mask Register */
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AT91_REG TWI_RHR; /* Receive Holding Register */
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AT91_REG TWI_THR; /* Transmit Holding Register */
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AT91_REG Reserved1[50];
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AT91_REG TWI_RPR; /* Receive Pointer Register */
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AT91_REG TWI_RCR; /* Receive Counter Register */
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AT91_REG TWI_TPR; /* Transmit Pointer Register */
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AT91_REG TWI_TCR; /* Transmit Counter Register */
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AT91_REG TWI_RNPR; /* Receive Next Pointer Register */
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AT91_REG TWI_RNCR; /* Receive Next Counter Register */
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AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */
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AT91_REG TWI_TNCR; /* Transmit Next Counter Register */
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AT91_REG TWI_PTCR; /* PDC Transfer Control Register */
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AT91_REG TWI_PTSR; /* PDC Transfer Status Register */
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} AT91S_TWI, *AT91PS_TWI;
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#endif
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/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
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#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */
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#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */
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#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */
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#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */
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#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */
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#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */
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#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */
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/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
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#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */
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#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */
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#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */
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#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */
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#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */
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#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */
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#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */
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/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
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#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */
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/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
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#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */
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#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */
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#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */
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/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
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#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */
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#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */
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#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/
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#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */
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#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */
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#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */
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#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */
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#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */
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#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */
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#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */
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/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
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/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
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/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
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/*
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i2c Support for Atmel's AT91RM9200 Two-Wire Interface
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(c) Rick Bronson
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_I2C_H
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#define AT91_I2C_H
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#define AT91C_TWI_CLOCK 100000
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#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
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#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */
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#if (AT91C_TWI_SCLOCK % 10) >= 5
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#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
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#else
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#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
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#endif
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#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
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#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16)
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#endif /* __ASSEMBLY__ */
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#endif /* AT91RM9200_TWI_H */
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