upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
3.7 KiB
118 lines
3.7 KiB
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SPARTAN3_H_
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#define _SPARTAN3_H_
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#include <xilinx.h>
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extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
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extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
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extern int Spartan3_info(Xilinx_desc *desc);
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/* Slave Parallel Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_init_fn init;
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Xilinx_err_fn err;
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Xilinx_done_fn done;
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Xilinx_clk_fn clk;
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Xilinx_cs_fn cs;
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Xilinx_wr_fn wr;
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Xilinx_rdata_fn rdata;
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Xilinx_wdata_fn wdata;
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Xilinx_busy_fn busy;
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Xilinx_abort_fn abort;
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Xilinx_post_fn post;
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} Xilinx_Spartan3_Slave_Parallel_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_clk_fn clk;
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Xilinx_init_fn init;
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Xilinx_done_fn done;
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Xilinx_wr_fn wr;
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Xilinx_post_fn post;
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Xilinx_bwr_fn bwr; /* block write function */
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Xilinx_abort_fn abort;
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} Xilinx_Spartan3_Slave_Serial_fns;
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/* Device Image Sizes
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*********************************************************************/
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/* Spartan-III (1.2V) */
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#define XILINX_XC3S50_SIZE 439264/8
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#define XILINX_XC3S200_SIZE 1047616/8
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#define XILINX_XC3S400_SIZE 1699136/8
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#define XILINX_XC3S1000_SIZE 3223488/8
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#define XILINX_XC3S1500_SIZE 5214784/8
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#define XILINX_XC3S2000_SIZE 7673024/8
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#define XILINX_XC3S4000_SIZE 11316864/8
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#define XILINX_XC3S5000_SIZE 13271936/8
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/* Spartan-3E (v3.4) */
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#define XILINX_XC3S100E_SIZE 581344/8
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#define XILINX_XC3S250E_SIZE 1353728/8
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#define XILINX_XC3S500E_SIZE 2270208/8
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#define XILINX_XC3S1200E_SIZE 3841184/8
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#define XILINX_XC3S1600E_SIZE 5969696/8
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/*
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* Spartan-6 : the Spartan-6 family can be programmed
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* exactly as the Spartan-3
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*/
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#define XILINK_XC6SLX4_SIZE (3713568/8)
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/* Descriptor Macros
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*********************************************************************/
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/* Spartan-III devices */
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#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
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#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
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#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
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#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
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#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
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#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
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#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
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#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
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/* Spartan-3E devices */
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#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
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#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
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#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
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#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
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#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
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#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
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#endif /* _SPARTAN3_H_ */
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