upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
1.2 KiB
60 lines
1.2 KiB
/*
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* Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
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*
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* Copyright 2005-2009 Analog Devices Inc.
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* 2005 BuyWays BV
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* Bas Vermeulen <bas@buyways.nl>
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*
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* Licensed under the GPL-2.
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*/
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#include <asm/linkage.h>
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.align 2
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ENTRY(_outsl)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
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.Llong_loop_s: R0 = [P1++];
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.Llong_loop_e: [P0] = R0;
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RTS;
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ENDPROC(_outsl)
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ENTRY(_outsw)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
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.Lword_loop_s: R0 = W[P1++];
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.Lword_loop_e: W[P0] = R0;
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RTS;
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ENDPROC(_outsw)
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ENTRY(_outsb)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
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.Lbyte_loop_s: R0 = B[P1++];
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.Lbyte_loop_e: B[P0] = R0;
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RTS;
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ENDPROC(_outsb)
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ENTRY(_outsw_8)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
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.Lword8_loop_s: R1 = B[P1++];
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R0 = B[P1++];
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R0 = R0 << 8;
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R0 = R0 + R1;
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.Lword8_loop_e: W[P0] = R0;
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RTS;
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ENDPROC(_outsw_8)
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