upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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492 lines
14 KiB
492 lines
14 KiB
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC830x 1 /* MPC830x family */
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#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
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/*
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* On-board devices
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*
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* TSECs
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*/
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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/*
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* Hardware Reset Configuration Word
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* if CLKIN is 66.66MHz, then
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* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
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* We choose the A type silicon as default, so the core is 400Mhz.
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_SVCOD_DIV_2 |\
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HRCWL_CSB_TO_CLKIN_4X1 |\
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HRCWL_CORE_TO_CSB_3X1)
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/*
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* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
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* in 8308's HRCWH according to the manual, but original Freescale's
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* code has them and I've expirienced some problems using the board
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* with BDI3000 attached when I've tried to set these bits to zero
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* (UART doesn't work after the 'reset run' command).
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*/
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_MII |\
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HRCWH_TSEC2M_IN_MII |\
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HRCWH_BIG_ENDIAN)
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/*
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* System IO Config
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*/
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#define CONFIG_SYS_SICRH (\
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SICRH_ESDHC_A_GPIO |\
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SICRH_ESDHC_B_GPIO |\
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SICRH_ESDHC_C_GTM |\
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SICRH_GPIO_A_TSEC2 |\
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SICRH_GPIO_B_TSEC2_TX_CLK |\
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SICRH_IEEE1588_A_GPIO |\
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SICRH_USB |\
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SICRH_GTM_GPIO |\
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SICRH_IEEE1588_B_GPIO |\
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SICRH_ETSEC2_CRS |\
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SICRH_GPIOSEL_1 |\
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SICRH_TMROBI_V3P3 |\
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SICRH_TSOBI1_V3P3 |\
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SICRH_TSOBI2_V3P3) /* 0xf577d100 */
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#define CONFIG_SYS_SICRL (\
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SICRL_SPI_PF0 |\
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SICRL_UART_PF0 |\
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SICRL_IRQ_PF0 |\
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SICRL_I2C2_PF0 |\
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SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
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#define CONFIG_SYS_GPIO1_PRELIM
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/* GPIO Default input/output settings */
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#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
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/*
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* Default GPIO values:
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* LED#1 enabled; WLAN enabled; Both COM LED on (orange)
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*/
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#define CONFIG_SYS_GPIO1_DAT 0x08008C00
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* SERDES
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*/
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_LOZ \
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| DDRCDR_NZ_LOZ \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x7b880001 */
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/*
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* Manually set up DDR parameters
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* consist of two chips HY5PS12621BFP-C4 from HYNIX
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80010102 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00220802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (6 << TIMING_CFG1_REFREC_SHIFT) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x27256222 */
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (4 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x121048c5 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03600100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_32)
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/* 0x43080000 */
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0232 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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/*
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* Memory test
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*/
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#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x07f00000
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| BR_PS_16 /* 16 bit port */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_4 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
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/* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
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/*
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* SJA1000 CAN controller on Local Bus
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*/
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#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
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| BR_PS_8 /* 8 bit port size */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
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| OR_GPCM_SCY_5 \
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| OR_GPCM_EHTR_SET)
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/* 0xFFFF8052 */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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/*
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* CPLD on Local Bus
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*/
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#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
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| BR_PS_8 /* 8 bit port */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
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| OR_GPCM_SCY_4 \
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| OR_GPCM_EHTR_SET)
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/* 0xFFFF8042 */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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/*
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* Serial Port
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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/* enable PCIE clock */
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#define CONFIG_SYS_SCCR_PCIEXP1CM 1
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCIE
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
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/*
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* TSEC
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*/
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 1
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#define TSEC2_PHY_ADDR 2
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS 0
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#define TSEC2_FLAGS 0
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/* Options are: eTSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC0"
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/*
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* Environment
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*/
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/*
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* Core HID Setup
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*/
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE | \
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HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
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#define CONFIG_SYS_HID2 HID2_HBE
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/*
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* MMU Setup
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*/
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#endif
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs}" \
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" console=${consoledev},${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addmisc=setenv bootargs ${bootargs}\0" \
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"kernel_addr=FC0A0000\0" \
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"fdt_addr=FC2A0000\0" \
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"ramdisk_addr=FC2C0000\0" \
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"u-boot=mpc8308_p1m/u-boot.bin\0" \
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"kernel_addr_r=1000000\0" \
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"fdt_addr_r=C00000\0" \
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"hostname=mpc8308_p1m\0" \
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"bootfile=mpc8308_p1m/uImage\0" \
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"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
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"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
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"flash_self=run ramargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"bootcmd=run flash_self\0" \
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"load=tftp ${loadaddr} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
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" +${filesize};cp.b ${fileaddr} " \
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__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
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"upd=run load update\0" \
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#endif /* __CONFIG_H */
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