upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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516 lines
14 KiB
516 lines
14 KiB
#include <common.h>
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#include <pci.h>
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#include <74xx_7xx.h>
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#ifdef DEBUG
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#undef DEBUG
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#endif
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#ifdef DEBUG
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#define PRINTF(format, args...) _printf(format , ## args)
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#else
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#define PRINTF(format, argc...)
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#endif
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static pci_dev_t to_pci(int bus, int devfn)
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{
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return PCI_BDF(bus, (devfn>>3), devfn&3);
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}
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int mypci_find_device(int vendor, int product, int index)
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{
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return pci_find_device(vendor, product, index);
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}
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int mypci_bus(int device)
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{
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return PCI_BUS(device);
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}
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int mypci_devfn(int device)
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{
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return (PCI_DEV(device)<<3) | PCI_FUNC(device);
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}
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#define mypci_read_func(type, size) \
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type mypci_read_cfg_##size##(int bus, int devfn, int offset) \
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{ \
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type c; \
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pci_read_config_##size##(to_pci(bus, devfn), offset, &c); \
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return c; \
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}
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#define mypci_write_func(type, size) \
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void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value) \
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{ \
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pci_write_config_##size##(to_pci(bus, devfn), offset, value); \
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}
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mypci_read_func(u8,byte);
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mypci_read_func(u16,word);
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mypci_write_func(u8,byte);
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mypci_write_func(u16,word);
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u32 mypci_read_cfg_long(int bus, int devfn, int offset)
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{
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u32 c;
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pci_read_config_dword(to_pci(bus, devfn), offset, &c);
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return c;
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}
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void mypci_write_cfg_long(int bus, int devfn, int offset, int value)
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{
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pci_write_config_dword(to_pci(bus, devfn), offset, value);
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}
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void _printf(const char *fmt, ...)
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{
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va_list args;
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char buf[CFG_PBSIZE];
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va_start(args, fmt);
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(void)vsprintf(buf, fmt, args);
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va_end(args);
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printf(buf);
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}
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char *_getenv(char *name)
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{
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return getenv(name);
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}
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unsigned long get_bar_size(pci_dev_t dev, int offset)
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{
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u32 bar_back, bar_value;
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/* Save old BAR value */
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pci_read_config_dword(dev, offset, &bar_back);
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/* Write all 1's. */
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pci_write_config_dword(dev, offset, ~0);
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/* Now read back the relevant bits */
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pci_read_config_dword(dev, offset, &bar_value);
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/* Restore original value */
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pci_write_config_dword(dev, offset, bar_back);
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if (bar_value == 0) return 0xFFFFFFFF; /* This BAR is disabled */
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if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY)
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{
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/* This is a memory space BAR. Mask it out so we get the size of it */
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return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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}
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/* Not suitable */
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return 0xFFFFFFFF;
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}
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void enable_compatibility_hole(void)
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{
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u8 cfg;
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pci_dev_t art = PCI_BDF(0,0,0);
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pci_read_config_byte(art, 0x54, &cfg);
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/* cfg |= 0x08; */
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cfg |= 0x20;
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pci_write_config_byte(art, 0x54, cfg);
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}
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void disable_compatibility_hole(void)
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{
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u8 cfg;
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pci_dev_t art = PCI_BDF(0,0,0);
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pci_read_config_byte(art, 0x54, &cfg);
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/* cfg &= ~0x08; */
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cfg &= ~0x20;
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pci_write_config_byte(art, 0x54, cfg);
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}
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void map_rom(pci_dev_t dev, u32 address)
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{
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE);
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}
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void unmap_rom(pci_dev_t dev)
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{
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
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}
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void bat_map(u8 batnum, u32 address, u32 length)
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{
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u32 temp = address;
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address &= 0xFFFE0000;
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temp &= 0x0001FFFF;
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length = (length - 1 ) >> 17;
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length <<= 2;
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switch (batnum)
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{
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case 0:
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__asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
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__asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
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break;
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case 1:
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__asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
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__asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
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break;
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case 2:
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__asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
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__asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
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break;
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case 3:
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__asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
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__asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
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break;
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}
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}
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int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size);
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int attempt_map_rom(pci_dev_t dev, void *copy_address)
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{
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u32 rom_size = 0;
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u32 rom_address = 0;
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u32 bar_size = 0;
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u32 bar_backup = 0;
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int i,j;
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void *image = 0;
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u32 image_size = 0;
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int did_correct = 0;
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u32 prefetch_addr = 0;
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u32 prefetch_size = 0;
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u32 prefetch_idx = 0;
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/* Get the size of the expansion rom */
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF);
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pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size);
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if ((rom_size & 0x01) == 0)
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{
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PRINTF("No ROM\n");
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return 0;
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}
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rom_size &= 0xFFFFF800;
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rom_size = (~rom_size)+1;
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PRINTF("ROM Size is %dK\n", rom_size/1024);
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/*
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* Try to find a place for the ROM. We always attempt to use
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* one of the card's bases for this, as this will be in any
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* bridge's resource range as well as being free of conflicts
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* with other cards. In a graphics card it is very unlikely
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* that there won't be any base address that is large enough to
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* hold the rom.
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*
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* FIXME: To work around this, theoretically the largest base
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* could be used if none is found in the loop below.
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*/
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for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
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{
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bar_size = get_bar_size(dev, i);
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PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n",
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(i - PCI_BASE_ADDRESS_0)/4,
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bar_size/1024);
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if (bar_size != 0xFFFFFFFF && bar_size >= rom_size)
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{
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PRINTF("Found a match for rom size\n");
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pci_read_config_dword(dev, i, &rom_address);
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rom_address &= 0xFFFFFFF0;
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if (rom_address != 0 && rom_address != 0xFFFFFFF0) break;
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}
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}
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if (rom_address == 0 || rom_address == 0xFFFFFFF0)
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{
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PRINTF("No suitable rom address found\n");
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return 0;
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}
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/* Disable the BAR */
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pci_read_config_dword(dev, i, &bar_backup);
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pci_write_config_dword(dev, i, 0);
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/* Map ROM */
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE);
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/* Copy the rom to a place in the emulator space */
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PRINTF("Claiming BAT 2\n");
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bat_map(2, rom_address, rom_size);
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/* show_bat_mapping(); */
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if (0 == find_image(rom_address, rom_size, &image, &image_size))
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{
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PRINTF("No x86 BIOS image found\n");
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return 0;
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}
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PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address);
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/* memcpy(copy_address, rom_address, rom_size); */
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{
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unsigned char *from = (unsigned char *)image; /* rom_address; */
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unsigned char *to = (unsigned char *)copy_address;
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for (j=0; j<image_size /*rom_size*/; j++)
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{
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*to++ = *from++;
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}
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}
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PRINTF("Copy is done\n");
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/* Unmap the ROM and restore the BAR */
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
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pci_write_config_dword(dev, i, bar_backup);
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/* FIXME: Shouldn't be needed anymore*/
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/* bat_map(2, 0x80000000, 256*1024*1024);
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show_bat_mapping(); */
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/*
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* Since most cards can probably only do 16 bit IO addressing, we
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* correct their IO base into an appropriate value.
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* This should do for most.
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*/
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for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
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{
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unsigned long value;
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pci_read_config_dword(dev, i, &value);
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if (value & 0x01) /* IO */
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{
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did_correct = 1;
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pci_write_config_dword(dev, i, 0x1001);
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break;
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}
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if (value & PCI_BASE_ADDRESS_MEM_PREFETCH)
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{
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prefetch_idx = i;
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prefetch_addr = value & PCI_BASE_ADDRESS_MEM_MASK;
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prefetch_size = get_bar_size(dev, i);
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}
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}
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if (1) /* did_correct) */
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{
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extern pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr);
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int busnr = PCI_BUS(dev);
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if (busnr)
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{
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pci_dev_t bridge;
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PRINTF("Need to correct bridge device for IO range change\n");
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bridge = pci_find_bridge_for_bus(NULL, busnr);
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if (bridge == PCI_ANY_ID)
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{
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PRINTF("Didn't find bridge. Hope that's OK\n");
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}
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else
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{
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/*
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* Set upper I/O base/limit to 0
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*/
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pci_write_config_byte(bridge, 0x30, 0x00);
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pci_write_config_byte(bridge, 0x31, 0x00);
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pci_write_config_byte(bridge, 0x32, 0x00);
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pci_write_config_byte(bridge, 0x33, 0x00);
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if (did_correct)
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{
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/*
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* set lower I/O base to 1000
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* That is, bits 0:3 are set to 0001 by default.
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* bits 7:4 contain I/O address bits 15:12
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* all others are assumed 0.
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*/
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pci_write_config_byte(bridge, 0x1C, 0x11);
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/*
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* Set lower I/O limit to 1FFF
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* That is, bits 0:3 are reserved and always 0000
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* Bits 7:4 contain I/O address bits 15:12
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* All others are assumed F.
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*/
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pci_write_config_byte(bridge, 0x1D, 0x10);
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pci_write_config_byte(bridge, 0x0D, 0x20);
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PRINTF("Corrected bridge resource range of bridge at %02x:%02x:%02x\n",
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PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
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}
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else
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{
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/*
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* This card doesn't have I/O, we disable I/O forwarding
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*/
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pci_write_config_byte(bridge, 0x1C, 0x11);
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pci_write_config_byte(bridge, 0x1D, 0x00);
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pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
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pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
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pci_write_config_dword(bridge, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_IO);
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PRINTF("Disabled bridge resource range of bridge at %02x:%02x:%02x\n",
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PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
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}
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}
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/*
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* Correct the prefetchable memory base, which is not set correctly by
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* the U-Boot autoconfig stuff
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*/
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if (prefetch_idx)
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{
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/* PRINTF("Setting prefetchable range to %x, %x (%x and %x)\n", */
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/* prefetch_addr, prefetch_addr+prefetch_size, */
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/* prefetch_addr>>16, (prefetch_addr+prefetch_size)>>16); */
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/* pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */
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/* pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */
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}
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pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000);
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pci_write_config_byte(bridge, 0xD0, 0x0A);
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pci_write_config_byte(bridge, 0xD3, 0x04);
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/*
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* Set the interrupt pin to 0
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*/
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#if 0
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0);
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pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0);
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#endif
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pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
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pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
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}
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}
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/* Finally, enable the card's IO and memory response */
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pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
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return 1;
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}
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int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size)
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{
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int i = 0;
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unsigned char *rom = (unsigned char *)rom_address;
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/* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; // No bios rom this is, yes. */
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for (;;)
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{
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unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19);
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unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512;
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unsigned char pci_image_type = *(rom+pci_data_offset+0x14);
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if (*rom != 0x55 || *(rom+1) != 0xAA)
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{
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PRINTF("Invalid header this is\n");
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return 0;
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}
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PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type,
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pci_image_type==0 ? "x86" :
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pci_image_type==1 ? "OpenFirmware" :
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"Unknown");
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if (pci_image_type == 0)
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{
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*image = rom;
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*image_size = pci_image_length;
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return 1;
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}
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if (*(rom+pci_data_offset+0x15) & 0x80)
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{
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PRINTF("LAST image encountered, no image found\n");
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return 0;
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}
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rom += pci_image_length;
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}
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}
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void show_bat_mapping(void)
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{
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u32 dbat0u, dbat0l, ibat0u, ibat0l;
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u32 dbat1u, dbat1l, ibat1u, ibat1l;
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u32 dbat2u, dbat2l, ibat2u, ibat2l;
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u32 dbat3u, dbat3l, ibat3u, ibat3l;
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u32 msr, hid0, l2cr_reg;
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__asm volatile ("mfdbatu %0,0" : "=r" (dbat0u));
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__asm volatile ("mfdbatl %0,0" : "=r" (dbat0l));
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__asm volatile ("mfibatu %0,0" : "=r" (ibat0u));
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__asm volatile ("mfibatl %0,0" : "=r" (ibat0l));
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__asm volatile ("mfdbatu %0,1" : "=r" (dbat1u));
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__asm volatile ("mfdbatl %0,1" : "=r" (dbat1l));
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__asm volatile ("mfibatu %0,1" : "=r" (ibat1u));
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__asm volatile ("mfibatl %0,1" : "=r" (ibat1l));
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__asm volatile ("mfdbatu %0,2" : "=r" (dbat2u));
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__asm volatile ("mfdbatl %0,2" : "=r" (dbat2l));
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__asm volatile ("mfibatu %0,2" : "=r" (ibat2u));
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__asm volatile ("mfibatl %0,2" : "=r" (ibat2l));
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__asm volatile ("mfdbatu %0,3" : "=r" (dbat3u));
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__asm volatile ("mfdbatl %0,3" : "=r" (dbat3l));
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__asm volatile ("mfibatu %0,3" : "=r" (ibat3u));
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__asm volatile ("mfibatl %0,3" : "=r" (ibat3l));
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__asm volatile ("mfmsr %0" : "=r" (msr));
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__asm volatile ("mfspr %0,1008": "=r" (hid0));
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__asm volatile ("mfspr %0,1017": "=r" (l2cr_reg));
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printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n",
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dbat0u, dbat0l, ibat0u, ibat0l);
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printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n",
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dbat1u, dbat1l, ibat1u, ibat1l);
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printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n",
|
|
dbat2u, dbat2l, ibat2u, ibat2l);
|
|
printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n",
|
|
dbat3u, dbat3l, ibat3u, ibat3l);
|
|
|
|
printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg);
|
|
}
|
|
|
|
|
|
|
|
void remove_init_data(void)
|
|
{
|
|
char *s;
|
|
|
|
/* Invalidate and disable data cache */
|
|
invalidate_l1_data_cache();
|
|
dcache_disable();
|
|
|
|
s = getenv("x86_cache");
|
|
|
|
if (!s)
|
|
{
|
|
icache_enable();
|
|
dcache_enable();
|
|
}
|
|
else if (s)
|
|
{
|
|
if (strcmp(s, "dcache")==0)
|
|
{
|
|
dcache_enable();
|
|
}
|
|
else if (strcmp(s, "icache") == 0)
|
|
{
|
|
icache_enable();
|
|
}
|
|
else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
|
|
{
|
|
dcache_enable();
|
|
icache_enable();
|
|
}
|
|
}
|
|
|
|
/* show_bat_mapping();*/
|
|
}
|
|
|