upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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90 lines
1.9 KiB
90 lines
1.9 KiB
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <smbios.h>
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#include <asm/sfi.h>
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#include <asm/mpspec.h>
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#include <asm/tables.h>
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#include <asm/acpi_table.h>
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#include <asm/coreboot_tables.h>
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/**
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* Function prototype to write a specific configuration table
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*
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* @addr: start address to write the table
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* @return: end address of the table
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*/
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typedef ulong (*table_write)(ulong addr);
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static table_write table_write_funcs[] = {
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#ifdef CONFIG_GENERATE_PIRQ_TABLE
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write_pirq_routing_table,
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#endif
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#ifdef CONFIG_GENERATE_SFI_TABLE
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write_sfi_table,
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#endif
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#ifdef CONFIG_GENERATE_MP_TABLE
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write_mp_table,
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#endif
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#ifdef CONFIG_GENERATE_ACPI_TABLE
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write_acpi_tables,
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#endif
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#ifdef CONFIG_GENERATE_SMBIOS_TABLE
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write_smbios_table,
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#endif
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};
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void table_fill_string(char *dest, const char *src, size_t n, char pad)
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{
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int start, len;
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int i;
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strncpy(dest, src, n);
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/* Fill the remaining bytes with pad */
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len = strlen(src);
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start = len < n ? len : n;
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for (i = start; i < n; i++)
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dest[i] = pad;
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}
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void write_tables(void)
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{
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u32 rom_table_start = ROM_TABLE_ADDR;
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u32 rom_table_end;
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#ifdef CONFIG_SEABIOS
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u32 high_table, table_size;
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struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
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#endif
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int i;
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for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
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rom_table_end = table_write_funcs[i](rom_table_start);
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rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
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#ifdef CONFIG_SEABIOS
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table_size = rom_table_end - rom_table_start;
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high_table = (u32)high_table_malloc(table_size);
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if (high_table) {
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table_write_funcs[i](high_table);
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cfg_tables[i].start = high_table;
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cfg_tables[i].size = table_size;
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} else {
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printf("%d: no memory for configuration tables\n", i);
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}
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#endif
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rom_table_start = rom_table_end;
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}
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#ifdef CONFIG_SEABIOS
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/* make sure the last item is zero */
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cfg_tables[i].size = 0;
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write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
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#endif
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}
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