upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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120 lines
2.9 KiB
120 lines
2.9 KiB
/*
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* Based on the iomux-v3.c from Linux kernel:
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
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#include <asm/arch/sys_proto.h>
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#endif
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#include <asm/imx-common/iomux-v3.h>
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static void *base = (void *)IOMUXC_BASE_ADDR;
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/*
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* configures a single pad in the iomuxer
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*/
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void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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{
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u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 sel_input_ofs =
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(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 sel_input =
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(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 pad_ctrl_ofs =
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(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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#if defined CONFIG_MX6SL
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/* Check whether LVE bit needs to be set */
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if (pad_ctrl & PAD_CTL_LVE) {
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pad_ctrl &= ~PAD_CTL_LVE;
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pad_ctrl |= PAD_CTL_LVE_BIT;
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}
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#endif
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if (mux_ctrl_ofs)
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__raw_writel(mux_mode, base + mux_ctrl_ofs);
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if (sel_input_ofs)
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__raw_writel(sel_input, base + sel_input_ofs);
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#ifdef CONFIG_IOMUX_SHARE_CONF_REG
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if (!(pad_ctrl & NO_PAD_CTRL))
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__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
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base + pad_ctrl_ofs);
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#else
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if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
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#endif
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}
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/* configures a list of pads within declared with IOMUX_PADS macro */
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void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
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unsigned count)
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{
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iomux_v3_cfg_t const *p = pad_list;
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int stride;
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int i;
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#if defined(CONFIG_MX6QDL)
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stride = 2;
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if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
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p += 1;
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#else
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stride = 1;
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#endif
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for (i = 0; i < count; i++) {
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imx_iomux_v3_setup_pad(*p);
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p += stride;
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}
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}
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void imx_iomux_set_gpr_register(int group, int start_bit,
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int num_bits, int value)
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{
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int i = 0;
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u32 reg;
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reg = readl(base + group * 4);
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while (num_bits) {
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reg &= ~(1<<(start_bit + i));
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i++;
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num_bits--;
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}
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reg |= (value << start_bit);
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writel(reg, base + group * 4);
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}
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#ifdef CONFIG_IOMUX_SHARE_CONF_REG
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void imx_iomux_gpio_set_direction(unsigned int gpio,
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unsigned int direction)
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{
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u32 reg;
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/*
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* Only on Vybrid the input/output buffer enable flags
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* are part of the shared mux/conf register.
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*/
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reg = readl(base + (gpio << 2));
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if (direction)
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reg |= 0x2;
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else
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reg &= ~0x2;
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writel(reg, base + (gpio << 2));
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}
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void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
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{
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*gpio_state = readl(base + (gpio << 2)) &
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((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
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}
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#endif
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