upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
2.6 KiB
77 lines
2.6 KiB
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Header file for the Marvell's Feroceon CPU core.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MVEBU_SOC_H
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#define _MVEBU_SOC_H
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#define SOC_MV78460_ID 0x7846
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#define SOC_88F6810_ID 0x6810
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#define SOC_88F6820_ID 0x6820
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#define SOC_88F6828_ID 0x6828
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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/* TCLK Core Clock definition */
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#ifndef CONFIG_SYS_TCLK
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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#endif
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
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/*
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* On A38x switching the regs base address without running from
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* SDRAM doesn't seem to work. So let the SPL still use the
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* default base address and switch to the new address in the
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* main u-boot later.
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*/
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#define SOC_REGS_PHY_BASE 0xd0000000
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#else
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#define SOC_REGS_PHY_BASE 0xf1000000
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#endif
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
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#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
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#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
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#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
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#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
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#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
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#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
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#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
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#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
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#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
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#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
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#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
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#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
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#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
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#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
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#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
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#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
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#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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/* MVEBU CPU memory windows */
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#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
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#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
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#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
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#endif /* _MVEBU_SOC_H */
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