upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
1.6 KiB
71 lines
1.6 KiB
/*
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* (C) Copyright 2009 Alessandro Rubini
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mtu.h>
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/*
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* The timer is a decrementer, we'll left it free running at 2.4MHz.
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* We have 2.4 ticks per microsecond and an overflow in almost 30min
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*/
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#define TIMER_CLOCK (24 * 100 * 1000)
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#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
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#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
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#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
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#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
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/* macro to read the decrementing 32 bit timer as an increasing count */
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#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
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/* Configure a free-running, auto-wrap counter with no prescaler */
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int timer_init(void)
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{
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ulong val;
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writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
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CONFIG_SYS_TIMERBASE + MTU_CR(0));
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/* Reset the timer */
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writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
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/*
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* The load-register isn't really immediate: it changes on clock
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* edges, so we must wait for our newly-written value to appear.
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* Since we might miss reading 0, wait for any change in value.
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*/
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val = READ_TIMER();
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while (READ_TIMER() == val)
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;
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return 0;
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}
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/* Return how many HZ passed since "base" */
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ulong get_timer(ulong base)
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{
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return TICKS_TO_HZ(READ_TIMER()) - base;
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}
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/* Delay x useconds */
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void __udelay(unsigned long usec)
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{
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ulong ini, end;
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ini = READ_TIMER();
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end = ini + USEC_TO_COUNT(usec);
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while ((signed)(end - READ_TIMER()) > 0)
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;
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}
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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