upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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170 lines
3.6 KiB
170 lines
3.6 KiB
/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation,
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*/
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/*
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* File: serial.c
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*
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* Discription: Serial interface driver for SCI1 and SCI2.
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* Since this code will be called from ROM use
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* only non-static local variables.
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*
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc5xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Local function prototypes
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*/
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static int ready_to_send(void);
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/*
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* Minimal global serial functions needed to use one of the SCI modules.
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*/
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int serial_init (void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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serial_setbrg();
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#if defined(CONFIG_5xx_CONS_SCI1)
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/* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */
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immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10;
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immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
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#else
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immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
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immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE;
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#endif
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return 0;
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}
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void serial_putc(const char c)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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/* Test for completition */
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if(ready_to_send()) {
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#if defined(CONFIG_5xx_CONS_SCI1)
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immr->im_qsmcm.qsmcm_sc1dr = (short)c;
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#else
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immr->im_qsmcm.qsmcm_sc2dr = (short)c;
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#endif
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if(c == '\n') {
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if(ready_to_send());
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#if defined(CONFIG_5xx_CONS_SCI1)
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immr->im_qsmcm.qsmcm_sc1dr = (short)'\r';
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#else
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immr->im_qsmcm.qsmcm_sc2dr = (short)'\r';
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#endif
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}
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}
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}
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int serial_getc(void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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volatile short status;
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unsigned char tmp;
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/* New data ? */
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do {
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#if defined(CONFIG_5xx_CONS_SCI1)
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status = immr->im_qsmcm.qsmcm_sc1sr;
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#else
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status = immr->im_qsmcm.qsmcm_sc2sr;
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#endif
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#if defined(CONFIG_WATCHDOG)
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reset_5xx_watchdog (immr);
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#endif
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} while ((status & SCI_RDRF) == 0);
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/* Read data */
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#if defined(CONFIG_5xx_CONS_SCI1)
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tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK);
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#else
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tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK);
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#endif
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return tmp;
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}
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int serial_tstc()
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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short status;
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/* New data character ? */
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#if defined(CONFIG_5xx_CONS_SCI1)
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status = immr->im_qsmcm.qsmcm_sc1sr;
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#else
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status = immr->im_qsmcm.qsmcm_sc2sr;
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#endif
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return (status & SCI_RDRF);
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}
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void serial_setbrg (void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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short scxbr;
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/* Set baudrate */
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scxbr = (gd->cpu_clk / (32 * gd->baudrate));
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#if defined(CONFIG_5xx_CONS_SCI1)
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immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK);
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#else
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immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK);
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#endif
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}
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void serial_puts (const char *s)
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{
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while (*s) {
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serial_putc(*s);
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++s;
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}
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}
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int ready_to_send(void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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volatile short status;
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do {
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#if defined(CONFIG_5xx_CONS_SCI1)
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status = immr->im_qsmcm.qsmcm_sc1sr;
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#else
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status = immr->im_qsmcm.qsmcm_sc2sr;
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#endif
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#if defined(CONFIG_WATCHDOG)
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reset_5xx_watchdog (immr);
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#endif
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} while ((status & SCI_TDRE) == 0);
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return 1;
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}
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