upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
3.8 KiB
108 lines
3.8 KiB
/*
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* dramSetup.h
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*
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* Prototypes, etc. for the Motorola MPC8220
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* embedded cpu chips
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*
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* 2004 (c) Freescale, Inc.
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* Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __INCdramsetuph
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#define __INCdramsetuph
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#ifndef __ASSEMBLY__
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/* Where various things are in the SPD */
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#define LOC_TYPE 2
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#define LOC_CHECKSUM 63
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#define LOC_PHYS_BANKS 5
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#define LOC_LOGICAL_BANKS 17
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#define LOC_ROWS 3
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#define LOC_COLS 4
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#define LOC_WIDTH_HIGH 7
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#define LOC_WIDTH_LOW 6
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#define LOC_REFRESH 12
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#define LOC_BURSTS 16
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#define LOC_CAS 18
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#define LOC_CS 19
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#define LOC_WE 20
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#define LOC_Tcyc 9
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#define LOC_Tac 10
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#define LOC_Trp 27
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#define LOC_Trrd 28
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#define LOC_Trcd 29
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#define LOC_Tras 30
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#define LOC_Buffered 21
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/* Types of memory the SPD can tell us about.
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* We can actually only use SDRAM and DDR.
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*/
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#define TYPE_DRAM 1 /* plain old dram */
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#define TYPE_EDO 2 /* EDO dram */
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#define TYPE_Nibble 3 /* serial nibble memory */
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#define TYPE_SDR 4 /* SDRAM */
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#define TYPE_ROM 5 /* */
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#define TYPE_SGRRAM 6 /* graphics memory */
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#define TYPE_DDR 7 /* DDR sdram */
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#define SDRAMDS_MASK 0x3 /* each field is 2 bits wide */
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#define SDRAMDS_SBE_SHIFT 8 /* Clock enable drive strength */
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#define SDRAMDS_SBC_SHIFT 6 /* Clocks drive strength */
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#define SDRAMDS_SBA_SHIFT 4 /* Address drive strength */
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#define SDRAMDS_SBS_SHIFT 2 /* SDR DQS drive strength */
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#define SDRAMDS_SBD_SHIFT 0 /* Data and DQS drive strength */
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#define DRIVE_STRENGTH_HIGH 0
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#define DRIVE_STRENGTH_MED 1
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#define DRIVE_STRENGTH_LOW 2
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#define DRIVE_STRENGTH_OFF 3
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#define OK 0
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#define ERROR -1
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/* Structure to hold information about address muxing. */
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typedef struct tagMuxDescriptor {
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u8 MuxValue;
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u8 Columns;
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u8 Rows;
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u8 MoreColumns;
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} muxdesc_t;
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/* Structure to define one physical bank of
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* memory. Note that dram size in bytes is
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* (2^^(rows+columns)) * width * banks / 8
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*/
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typedef struct tagDramInfo {
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u32 size; /* size in bytes */
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u32 base; /* base address */
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u8 ordinal; /* where in the memory map will we put this */
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u8 type;
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u8 rows;
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u8 cols;
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u16 width; /* width of each chip in bits */
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u8 banks; /* number of chips, aka logical banks */
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u8 bursts; /* bit-encoded allowable burst length */
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u8 CAS; /* bit-encoded CAS latency values */
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u8 CS; /* bit-encoded CS latency values */
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u8 WE; /* bit-encoded WE latency values */
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u8 Trp; /* bit-encoded row precharge time */
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u8 Trcd; /* bit-encoded RAS to CAS delay */
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u8 buffered; /* buffered or not */
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u8 refresh; /* encoded refresh rate */
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} draminfo_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __INCdramsetuph */
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