upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
3.9 KiB
118 lines
3.9 KiB
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Gregory E. Allen, gallen@arlut.utexas.edu
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* Applied Research Laboratories, The University of Texas at Austin
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency on
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* PCI_SYNC_IN .
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*
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* CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240
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* boards. It should be defined as the PCI to Memory Multiplier as
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* documented in the MPC8240 Hardware Specs.
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*
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* Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER
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* because they can determine it from the PCR.
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*
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* Gary Milliorn <gary.milliorn@motorola.com> (who should know since
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* he designed the Sandpoint) told us that the PCR is not in all revs
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* of the MPC8240 CPU, so it's not guaranteeable and we cannot do
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* away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether.
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*/
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/* ------------------------------------------------------------------------- */
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/* This gives the PCI to Memory multiplier times 10 */
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/* The index is the value of PLL_CFG[0:4] */
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/* This is documented in the MPC8240/5 Hardware Specs */
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short pll_pci_to_mem_multiplier[] = {
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#if defined(CONFIG_MPC8240)
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30, 30, 10, 10, 20, 10, 0, 10,
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10, 0, 20, 0, 20, 0, 20, 0,
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30, 0, 15, 0, 20, 0, 20, 0,
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25, 0, 10, 0, 15, 15, 0, 0,
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#elif defined(CONFIG_MPC8245)
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30, 30, 10, 10, 20, 10, 10, 10,
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10, 20, 20, 15, 20, 15, 20, 30,
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30, 40, 15, 40, 20, 25, 20, 40,
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25, 20, 10, 20, 15, 15, 15, 0,
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#else
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#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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};
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#define CU824_PLL_STATE_REG 0xFE80002F
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#define PCR 0x800000E2
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/* ------------------------------------------------------------------------- */
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/* compute the memory bus clock frequency */
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ulong get_bus_freq (ulong dummy)
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{
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unsigned char pll_cfg;
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#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824)
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return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER);
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#elif defined(CONFIG_CU824)
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pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG);
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pll_cfg &= 0x1f;
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#else
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CONFIG_READ_BYTE(PCR, pll_cfg);
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pll_cfg = (pll_cfg >> 3) & 0x1f;
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#endif
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return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10;
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}
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/* ------------------------------------------------------------------------- */
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/* This gives the Memory to CPU Core multiplier times 10 */
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/* The index is the value of PLLRATIO in HID1 */
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/* This is documented in the MPC8240 Hardware Specs */
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/* This is not documented for MPC8245 ? FIXME */
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short pllratio_to_factor[] = {
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0, 0, 0, 10, 20, 20, 25, 45,
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30, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 10, 0, 0, 0, 45,
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30, 0, 40, 0, 0, 0, 35, 0,
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};
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/* compute the CPU and memory bus clock frequencies */
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int get_clocks (void)
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{
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uint hid1 = mfspr(HID1);
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hid1 = (hid1 >> (32-5)) & 0x1f;
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gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)
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/ 10;
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gd->bus_clk = get_bus_freq(0);
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return (0);
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}
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