upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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373 lines
11 KiB
373 lines
11 KiB
/*
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* (C) Copyright 2006-2009
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* Texas Instruments Incorporated.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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* Nishanth Menon <nm@ti.com>
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*
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* Configuration settings for the 3430 TI SDP3430 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* TODO: REMOVE THE FOLLOWING
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* Retained the following till size.h is removed in u-boot
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*/
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#include <asm/sizes.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */
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#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* NOTE: these #defines presume standard SDP jumper settings.
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* In particular:
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* - 26 MHz clock (not 19.2 or 38.4 MHz)
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* - Boot from 128MB NOR, not NAND or OneNAND
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*
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* At this writing, OMAP3 U-Boot support doesn't permit concurrent
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* support for all the flash types the board supports.
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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* Total Size Environment - 256k
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* Malloc - add 256k
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*/
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#define CONFIG_ENV_SIZE (256 << 10)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
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/* initial data */
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/*--------------------------------------------------------------------------*/
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/*
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* Hardware drivers
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*/
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_POWER 1
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/*
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* serial port - NS16550 compatible
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
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* swapped with UART2 via jumpering. Downsides of using J8: it doesn't
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* support UART boot (that's only for UART3); it prevents sharing a Linux
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* kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
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*
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* UART boot uses UART3 on J9, and the SDP user's guide says to use
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* that for console. Downsides of using J9: you can't use IRDA too;
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* since UART3 isn't in the CORE power domain, it may be a bit less
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* usable in certain PM-sensitive debug scenarios.
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*/
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#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
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#ifdef CONSOLE_J9
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 */
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#else
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 1 /* UART1 */
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#endif
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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/*
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* I2C for power management setup
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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/* DDR - I use Infineon DDR */
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#define CONFIG_OMAP3_INFINEON_DDR 1
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/* OMITTED: single 1 Gbit MT29F1G NAND flash */
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/*
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* NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
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*/
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#define CONFIG_SYS_FLASH_BASE 0x10000000
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CONFIG_SYS_FLASH_CFI_WIDTH 2
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#define PHYS_FLASH_SIZE (128 << 20)
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
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/* timeout values are in milliseconds */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
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#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
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/*--------------------------------------------------------------------------*/
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/* commands to include */
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#include <config_cmd_default.h>
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/* Enabled commands */
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#define CONFIG_CMD_DHCP /* DHCP Support */
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NET
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/* Disabled commands */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMLS /* List all found images */
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/*--------------------------------------------------------------------------*/
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/*
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* MMC boot support
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*/
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#if defined(CONFIG_CMD_MMC)
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#define CONFIG_MMC 1
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#define CONFIG_OMAP3_MMC 1
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#define CONFIG_DOS_PARTITION 1
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#endif
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/*----------------------------------------------------------------------------
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* SMSC9115 Ethernet from SMSC9118 family
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*----------------------------------------------------------------------------
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*/
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_NET_MULTI
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#define CONFIG_LAN91C96
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#define CONFIG_LAN91C96_BASE DEBUG_BASE
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#define CONFIG_LAN91C96_EXT_PHY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/*
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* BOOTP fields
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*/
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#define CONFIG_BOOTP_SUBNETMASK 0x00000001
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#define CONFIG_BOOTP_GATEWAY 0x00000002
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#define CONFIG_BOOTP_HOSTNAME 0x00000004
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#define CONFIG_BOOTP_BOOTPATH 0x00000010
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#endif /* (CONFIG_CMD_NET) */
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/*
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* Environment setup
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*
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* Default boot order: mmc bootscript, MMC uImage, NOR image.
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* Network booting environment must be configured at site.
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*/
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/* allow overwriting serial config and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyS0,115200n8\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait\0" \
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"norargs=setenv bootargs console=${console} " \
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"root=/dev/mtdblock3 rw " \
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"rootfstype=jffs2\0" \
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"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from MMC/SD ...; " \
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"autoscr ${loadaddr}\0" \
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"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from MMC/SD ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"norboot=echo Booting from NOR ...; " \
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"run norargs; " \
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"bootm 0x80000\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmcinit; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run norboot; " \
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"fi; " \
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"fi; " \
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"else run norboot; fi"
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#define CONFIG_AUTO_COMPLETE 1
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/*--------------------------------------------------------------------------*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
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* a basic sanity check ONLY
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* IF you would like to increase coverage, increase the end address
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* or run the test with custom options
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*/
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
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/* Default load address */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
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/*--------------------------------------------------------------------------*/
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/*
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* 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
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#endif
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/*
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* SDRAM Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C 1
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/*--------------------------------------------------------------------------*/
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/*
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* NOR FLASH usage ... default nCS0:
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* - one 256KB sector for U-Boot
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* - one 256KB sector for its parameters (not all used)
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* - eight sectors (2 MB) for kernel
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* - rest for JFFS2
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*/
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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/*
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* NAND FLASH usage ... default nCS1:
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* - four 128KB sectors for X-Loader
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* - four 128KB sectors for U-Boot
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* - two 128KB sector for its parameters
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* - 32 sectors (4 MB) for kernel
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* - rest for filesystem
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*/
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/*
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* OneNAND FLASH usage ... default nCS2:
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* - four 128KB sectors for X-Loader
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* - two 128KB sectors for U-Boot
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* - one 128KB sector for its parameters
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* - sixteen sectors (2 MB) for kernel
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* - rest for filesystem
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*/
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/*--------------------------------------------------------------------------*/
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#ifndef __ASSEMBLY__
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extern unsigned int boot_flash_base;
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extern volatile unsigned int boot_flash_env_addr;
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extern unsigned int boot_flash_off;
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extern unsigned int boot_flash_sec;
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extern unsigned int boot_flash_type;
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#endif
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#endif /* __CONFIG_H */
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