upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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705 lines
18 KiB
705 lines
18 KiB
/*
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* (C) Copyright 2002
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* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include "memio.h"
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#include "articiaS.h"
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#include "smbus.h"
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#include "via686.h"
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#undef DEBUG
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struct dimm_bank {
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uint8 used; /* Bank is populated */
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uint32 rows; /* Number of row addresses */
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uint32 columns; /* Number of column addresses */
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uint8 registered; /* SIMM is registered */
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uint8 ecc; /* SIMM has ecc */
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uint8 burst_len; /* Supported burst lengths */
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uint32 cas_lat; /* Supported CAS latencies */
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uint32 cas_used; /* CAS to use (not set by user) */
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uint32 trcd; /* RAS to CAS latency */
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uint32 trp; /* Precharge latency */
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uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */
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uint32 tclk_2hi; /* SDRAM second highest CAS latency */
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uint32 size; /* Size of bank in bytes */
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uint8 auto_refresh; /* Module supports auto refresh */
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uint32 refresh_time; /* Refresh time (in ns) */
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};
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/*
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** Based in part on the evb64260 code
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*/
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/*
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* translate ns.ns/10 coding of SPD timing values
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* into 10 ps unit values
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*/
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static inline unsigned short NS10to10PS (unsigned char spd_byte)
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{
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unsigned short ns, ns10;
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/* isolate upper nibble */
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ns = (spd_byte >> 4) & 0x0F;
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/* isolate lower nibble */
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ns10 = (spd_byte & 0x0F);
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return (ns * 100 + ns10 * 10);
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}
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/*
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* translate ns coding of SPD timing values
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* into 10 ps unit values
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*/
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static inline unsigned short NSto10PS (unsigned char spd_byte)
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{
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return (spd_byte * 100);
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}
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long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
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uint32 busclock = gd->bus_clk;
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uint32 memclock = busclock;
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uint32 tmemclock = 1000000000 / (memclock / 100);
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uint32 datawidth;
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if (sm_get_data (rom, dimm_address) == 0) {
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/* Nothing in slot, make both banks empty */
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debug ("Slot %d: vacant\n", dimmNum);
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banks[0].used = 0;
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banks[1].used = 0;
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return 0;
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}
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if (rom[2] != 0x04) {
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debug ("Slot %d: No SDRAM\n", dimmNum);
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banks[0].used = 0;
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banks[1].used = 0;
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return 0;
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}
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/* Determine number of banks/rows */
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if (rom[5] == 1) {
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banks[0].used = 1;
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banks[1].used = 0;
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} else {
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banks[0].used = 1;
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banks[1].used = 1;
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}
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/* Determine number of row addresses */
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if (rom[3] & 0xf0) {
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/* Different banks sizes */
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banks[0].rows = rom[3] & 0x0f;
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banks[1].rows = (rom[3] & 0xf0) >> 4;
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} else {
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/* Equal sized banks */
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banks[0].rows = rom[3] & 0x0f;
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banks[1].rows = banks[0].rows;
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}
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/* Determine number of column addresses */
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if (rom[4] & 0xf0) {
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/* Different bank sizes */
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banks[0].columns = rom[4] & 0x0f;
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banks[1].columns = (rom[4] & 0xf0) >> 4;
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} else {
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banks[0].columns = rom[4] & 0x0f;
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banks[1].columns = banks[0].columns;
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}
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/* Check Jedec revision, and modify row/column accordingly */
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if (rom[62] > 0x10) {
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if (banks[0].rows <= 3)
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banks[0].rows += 15;
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if (banks[1].rows <= 3)
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banks[1].rows += 15;
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if (banks[0].columns <= 3)
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banks[0].columns += 15;
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if (banks[0].columns <= 3)
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banks[0].columns += 15;
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}
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/* Check registered/unregisterd */
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if (rom[21] & 0x12) {
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banks[0].registered = 1;
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banks[1].registered = 1;
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} else {
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banks[0].registered = 0;
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banks[1].registered = 0;
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}
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#ifdef CONFIG_ECC
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/* Check parity/ECC */
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banks[0].ecc = (rom[11] == 0x02);
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banks[1].ecc = (rom[11] == 0x02);
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#endif
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/* Find burst lengths supported */
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banks[0].burst_len = rom[16] & 0x8f;
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banks[1].burst_len = rom[16] & 0x8f;
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/* Find possible cas latencies */
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banks[0].cas_lat = rom[18] & 0x7F;
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banks[1].cas_lat = rom[18] & 0x7F;
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/* RAS/CAS latency */
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banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
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banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
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/* Precharge latency */
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banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
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banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
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/* highest CAS latency */
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banks[0].tclk_hi = NS10to10PS (rom[9]);
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banks[1].tclk_hi = NS10to10PS (rom[9]);
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/* second highest CAS latency */
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banks[0].tclk_2hi = NS10to10PS (rom[23]);
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banks[1].tclk_2hi = NS10to10PS (rom[23]);
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/* bank sizes */
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datawidth = rom[13] & 0x7f;
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banks[0].size =
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(1L << (banks[0].rows + banks[0].columns)) *
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/* FIXME datawidth */ 8 * rom[17];
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if (rom[13] & 0x80)
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banks[1].size = 2 * banks[0].size;
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else
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banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
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/* FIXME datawidth */ 8 * rom[17];
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/* Refresh */
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if (rom[12] & 0x80) {
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banks[0].auto_refresh = 1;
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banks[1].auto_refresh = 1;
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} else {
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banks[0].auto_refresh = 0;
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banks[1].auto_refresh = 0;
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}
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switch (rom[12] & 0x7f) {
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case 0:
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banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
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break;
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case 1:
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banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
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break;
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case 2:
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banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
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break;
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case 3:
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banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
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break;
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case 4:
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banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
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break;
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case 5:
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banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
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banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
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break;
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default:
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banks[0].refresh_time = 0x100; /* Default of Articia S */
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banks[1].refresh_time = 0x100;
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break;
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}
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#ifdef DEBUG
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printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
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printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
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printf ("Number of row addresses: %ld\n", banks[0].rows);
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printf ("Number of coumns addresses: %ld\n", banks[0].columns);
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printf ("SIMM is %sregistered\n",
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banks[0].registered == 0 ? "not " : "");
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#ifdef CONFIG_ECC
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printf ("SIMM %s ECC\n",
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banks[0].ecc == 1 ? "supports" : "doesn't support");
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#endif
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printf ("Supported burst lenghts: %s %s %s %s %s\n",
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banks[0].burst_len & 0x08 ? "8" : " ",
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banks[0].burst_len & 0x04 ? "4" : " ",
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banks[0].burst_len & 0x02 ? "2" : " ",
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banks[0].burst_len & 0x01 ? "1" : " ",
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banks[0].burst_len & 0x80 ? "PAGE" : " ");
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printf ("Supported CAS latencies: %s %s %s\n",
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banks[0].cas_lat & 0x04 ? "CAS 3" : " ",
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banks[0].cas_lat & 0x02 ? "CAS 2" : " ",
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banks[0].cas_lat & 0x01 ? "CAS 1" : " ");
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printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
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printf ("Precharge latency: %ld\n", banks[0].trp);
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printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
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printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
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printf ("SDRAM data width: %ld\n", datawidth);
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printf ("Auto Refresh %ssupported\n",
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banks[0].auto_refresh ? "" : "not ");
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printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
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if (banks[0].used)
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printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
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if (banks[1].used)
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printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
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printf ("\n");
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#endif
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sm_term ();
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return 1;
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}
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void select_cas (struct dimm_bank *banks, uint8 fast)
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{
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if (!banks[0].used) {
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banks[0].cas_used = 0;
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banks[0].cas_used = 0;
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return;
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}
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if (fast) {
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/* Search for fast CAS */
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uint32 i;
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uint32 c = 0x01;
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for (i = 1; i < 5; i++) {
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if (banks[0].cas_lat & c) {
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banks[0].cas_used = i;
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banks[1].cas_used = i;
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debug ("Using CAS %d (fast)\n", i);
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return;
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}
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c <<= 1;
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}
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/* Default to CAS 3 */
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banks[0].cas_used = 3;
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banks[1].cas_used = 3;
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debug ("Using CAS 3 (fast)\n");
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return;
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} else {
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/* Search for slow cas */
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uint32 i;
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uint32 c = 0x08;
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for (i = 4; i > 1; i--) {
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if (banks[0].cas_lat & c) {
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banks[0].cas_used = i;
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banks[1].cas_used = i;
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debug ("Using CAS %d (slow)\n", i);
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return;
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}
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c >>= 1;
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}
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/* Default to CAS 3 */
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banks[0].cas_used = 3;
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banks[1].cas_used = 3;
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debug ("Using CAS 3 (slow)\n");
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return;
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}
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banks[0].cas_used = 3;
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banks[1].cas_used = 3;
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debug ("Using CAS 3\n");
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return;
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}
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uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
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{
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uint32 i;
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struct RowColumnSize {
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uint32 banks;
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uint32 rows;
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uint32 columns;
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uint32 size;
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uint32 register_value;
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};
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struct RowColumnSize rcs_map[] = {
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/* Sbk Radr Cadr MB Value */
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{1, 11, 8, 8, 0x00840f00},
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{1, 11, 9, 16, 0x00925f00},
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{1, 11, 10, 32, 0x00a64f00},
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{2, 12, 8, 32, 0x00c55f00},
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{2, 12, 9, 64, 0x00d66f00},
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{2, 12, 10, 128, 0x00e77f00},
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{2, 12, 11, 256, 0x00ff8f00},
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{2, 13, 11, 512, 0x00ff9f00},
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{0, 0, 0, 0, 0x00000000}
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};
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i = 0;
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while (rcs_map[i].banks != 0) {
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if (rows == rcs_map[i].rows
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&& columns == rcs_map[i].columns
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&& (size / 1024 / 1024) == rcs_map[i].size)
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return rcs_map[i].register_value;
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i++;
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}
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return 0;
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}
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uint32 burst_to_len (uint32 support)
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{
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if (support & 0x80)
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return 0x7;
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else if (support & 0x8)
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return 0x3;
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else if (support & 0x4)
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return 0x2;
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else if (support & 0x2)
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return 0x1;
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else if (support & 0x1)
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return 0x0;
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return 0;
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}
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long articiaS_ram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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register uint32 i;
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register uint32 value1;
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register uint32 value2;
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uint8 rom[128];
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uint32 burst_len;
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uint32 burst_support;
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uint32 total_ram = 0;
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struct dimm_bank banks[4]; /* FIXME: Move to initram */
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uint32 busclock = gd->bus_clk;
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uint32 memclock = busclock;
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uint32 reg32;
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uint32 refresh_clocks;
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uint8 auto_refresh;
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memset (banks, 0, sizeof (struct dimm_bank) * 4);
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detect_sdram (rom, 0, &banks[0]);
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detect_sdram (rom, 1, &banks[2]);
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for (i = 0; i < 4; i++) {
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total_ram = total_ram + (banks[i].used * banks[i].size);
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}
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pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
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pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
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pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */
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pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
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pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */
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pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */
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/* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
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if (banks[0].used) {
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value1 = get_reg_setting (banks[0].used + banks[1].used,
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banks[0].rows, banks[0].columns,
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banks[0].size);
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} else {
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value1 = 0;
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}
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if (banks[1].used) {
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value2 = get_reg_setting (banks[0].used + banks[1].used,
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banks[1].rows, banks[1].columns,
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banks[1].size);
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} else {
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value2 = 0;
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}
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pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
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pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
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debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
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debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
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if (banks[2].used) {
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value1 = get_reg_setting (banks[2].used + banks[3].used,
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banks[2].rows, banks[2].columns,
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banks[2].size);
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} else {
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value1 = 0;
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}
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if (banks[3].used) {
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value2 = get_reg_setting (banks[2].used + banks[3].used,
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banks[3].rows, banks[3].columns,
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banks[3].size);
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} else {
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value2 = 0;
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}
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pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
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pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
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debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
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debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
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pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
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pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
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pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
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pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
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/* Determine timing */
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select_cas (&banks[0], 0);
|
|
select_cas (&banks[2], 0);
|
|
|
|
/* FIXME: What about write recovery */
|
|
/* Auto refresh Precharge */
|
|
#if 0
|
|
reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
|
|
/* Write recovery CAS Latency */
|
|
(0x1 << 6) | (banks[0].cas_used << 4) |
|
|
/* RAS/CAS latency */
|
|
((banks[0].trcd - 1) << 0);
|
|
|
|
reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
|
|
(0x1 << 6) | (banks[2].cas_used << 4) |
|
|
((banks[2].trcd - 1) << 0)) << 16;
|
|
#else
|
|
if (100000000 == gd->bus_clk)
|
|
reg32 = 0x71737173;
|
|
else
|
|
reg32 = 0x69736973;
|
|
#endif
|
|
pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
|
|
debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
|
|
|
|
/* Write default in DIMM2/3 (not used on A1) */
|
|
pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
|
|
|
|
|
|
/* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
|
|
reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
|
|
reg32 &= 0xFF00FFFF;
|
|
|
|
#if 0
|
|
if (banks[0].used && banks[0].registered)
|
|
reg32 |= 0x1 << 16;
|
|
|
|
if (banks[2].used && banks[2].registered)
|
|
reg32 |= 0x1 << 18;
|
|
#else
|
|
if (banks[0].registered || banks[2].registered)
|
|
reg32 |= 0x55 << 16;
|
|
#endif
|
|
pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
|
|
debug ("DRAM_GCR0 = 0x%08x\n", reg32);
|
|
|
|
/* Determine refresh */
|
|
refresh_clocks = 0xffffffff;
|
|
auto_refresh = 1;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (banks[i].used) {
|
|
if (banks[i].auto_refresh == 0)
|
|
auto_refresh = 0;
|
|
if (banks[i].refresh_time < refresh_clocks)
|
|
refresh_clocks = banks[i].refresh_time;
|
|
}
|
|
}
|
|
|
|
|
|
#if 1
|
|
/* It seems this is suggested by the ArticiaS data book */
|
|
if (100000000 == gd->bus_clk)
|
|
refresh_clocks = 1561;
|
|
else
|
|
refresh_clocks = 2083;
|
|
#endif
|
|
|
|
|
|
debug ("Refresh set to %ld clocks, auto refresh %s\n",
|
|
refresh_clocks, auto_refresh ? "on" : "off");
|
|
|
|
pci_write_cfg_long (0, 0, DRAM_REFRESH0,
|
|
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
|
|
(refresh_clocks));
|
|
debug ("DRAM_REFRESH0 = 0x%08x\n",
|
|
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
|
|
(refresh_clocks));
|
|
|
|
/* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */
|
|
|
|
/* Set mode registers */
|
|
/* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
|
|
/* Find a common burst len */
|
|
burst_support = 0xff;
|
|
|
|
if (banks[0].used)
|
|
burst_support = banks[0].burst_len;
|
|
if (banks[1].used)
|
|
burst_support = banks[1].burst_len;
|
|
if (banks[2].used)
|
|
burst_support = banks[2].burst_len;
|
|
if (banks[3].used)
|
|
burst_support = banks[3].burst_len;
|
|
|
|
/*
|
|
** Mode register:
|
|
** Bits Use
|
|
** 0-2 Burst len
|
|
** 3 Burst type (0 = sequential, 1 = interleave)
|
|
** 4-6 CAS latency
|
|
** 7-8 Operation mode (0 = default, all others invalid)
|
|
** 9 Write burst
|
|
** 10-11 Reserved
|
|
**
|
|
** Mode register burst table:
|
|
** A2 A1 A0 lenght
|
|
** 0 0 0 1
|
|
** 0 0 1 2
|
|
** 0 1 0 4
|
|
** 0 1 1 8
|
|
** 1 0 0 invalid
|
|
** 1 0 1 invalid
|
|
** 1 1 0 invalid
|
|
** 1 1 1 page (only valid for non-interleaved)
|
|
*/
|
|
|
|
burst_len = burst_to_len (burst_support);
|
|
burst_len = 2; /* FIXME */
|
|
|
|
if (banks[0].used) {
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0,
|
|
0x8000 | burst_len | (banks[0].cas_used << 4));
|
|
debug ("Mode bank 0: 0x%08x\n",
|
|
0x8000 | burst_len | (banks[0].cas_used << 4));
|
|
} else {
|
|
/* Seems to be needed to disable the bank */
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
|
|
}
|
|
|
|
if (banks[1].used) {
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0,
|
|
0x9000 | burst_len | (banks[1].cas_used << 4));
|
|
debug ("Mode bank 1: 0x%08x\n",
|
|
0x8000 | burst_len | (banks[1].cas_used << 4));
|
|
} else {
|
|
/* Seems to be needed to disable the bank */
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
|
|
}
|
|
|
|
|
|
if (banks[2].used) {
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0,
|
|
0xa000 | burst_len | (banks[2].cas_used << 4));
|
|
debug ("Mode bank 2: 0x%08x\n",
|
|
0x8000 | burst_len | (banks[2].cas_used << 4));
|
|
} else {
|
|
/* Seems to be needed to disable the bank */
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
|
|
}
|
|
|
|
|
|
if (banks[3].used) {
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0,
|
|
0xb000 | burst_len | (banks[3].cas_used << 4));
|
|
debug ("Mode bank 3: 0x%08x\n",
|
|
0x8000 | burst_len | (banks[3].cas_used << 4));
|
|
} else {
|
|
/* Seems to be needed to disable the bank */
|
|
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
|
|
}
|
|
|
|
|
|
pci_write_cfg_word (0, 0, 0xba, 0x00);
|
|
|
|
return total_ram;
|
|
}
|
|
|
|
extern int drv_isa_kbd_init (void);
|
|
|
|
int last_stage_init (void)
|
|
{
|
|
drv_isa_kbd_init ();
|
|
return 0;
|
|
}
|
|
|
|
int overwrite_console (void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
#define in_8 read_byte
|
|
#define out_8 write_byte
|
|
|
|
static __inline__ unsigned long get_msr (void)
|
|
{
|
|
unsigned long msr;
|
|
|
|
asm volatile ("mfmsr %0":"=r" (msr):);
|
|
|
|
return msr;
|
|
}
|
|
|
|
static __inline__ void set_msr (unsigned long msr)
|
|
{
|
|
asm volatile ("mtmsr %0"::"r" (msr));
|
|
}
|
|
|
|
int board_pre_init (void)
|
|
{
|
|
unsigned char c_value = 0;
|
|
unsigned long msr;
|
|
|
|
/* Basic init of PS/2 keyboard (needed for some reason)... */
|
|
/* Ripped from John's code */
|
|
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
|
|
out_8 ((unsigned char *) 0xfe000064, 0xaa);
|
|
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
|
|
c_value = in_8 ((unsigned char *) 0xfe000060);
|
|
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
|
|
out_8 ((unsigned char *) 0xfe000064, 0xab);
|
|
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
|
|
c_value = in_8 ((unsigned char *) 0xfe000060);
|
|
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
|
|
out_8 ((unsigned char *) 0xfe000064, 0xae);
|
|
/* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
|
|
/* c_value = in_8((unsigned char *)0xfe000060); */
|
|
|
|
/* Enable FPU */
|
|
msr = get_msr ();
|
|
set_msr (msr | MSR_FP);
|
|
|
|
via_calibrate_bus_freq ();
|
|
|
|
return 0;
|
|
}
|
|
|