upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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127 lines
3.4 KiB
127 lines
3.4 KiB
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "ocrtc.h"
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#include <asm/processor.h>
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#include <i2c.h>
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#include <command.h>
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#include <cmd_boot.h>
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/* ------------------------------------------------------------------------- */
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int board_pre_init (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
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mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr (uictr, 0x10000000); /* set int trigger levels */
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: clear EBTC -> high-Z ebc signals between
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* transfers, set device-paced timeout to 256 cycles
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*/
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mtebc (epcr, 0x20400000);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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puts ("Board: ");
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if (i == -1) {
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#ifdef CONFIG_OCRTC
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puts ("### No HW ID - assuming OCRTC");
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#endif
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#ifdef CONFIG_ORSG
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puts ("### No HW ID - assuming ORSG");
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#endif
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} else {
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puts (str);
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr (memcfga, mem_mb0cf);
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val = mfdcr (memcfgd);
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#if 0
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printf ("\nmb0cf=%x\n", val); /* test-only */
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printf ("strap=%x\n", mfdcr (strap)); /* test-only */
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#endif
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return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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