upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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690 lines
19 KiB
690 lines
19 KiB
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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* TODO: clean-up
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*/
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/*
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* How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
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*
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* As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
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* used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
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* parameters from the datasheet are:
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* Tclk = 7.5ns (CL = 2)
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* Trp = 15ns
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* Trc = 60ns
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* Trcd = 15ns
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* Trfc = 66ns
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*
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* If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
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* period is 10ns and the parameters needed for the Timing Register are:
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* CASL = CL = 2 clock cycles
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* PTA = Trp = 15ns / 10ns = 2 clock cycles
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* CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
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* LDF = 2 clock cycles (but can be extended to meet board-level timing)
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* RFTA = Trfc = 66ns / 10ns= 7 clock cycles
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* RCD = Trcd = 15ns / 10ns= 2 clock cycles
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*
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* The actual bit settings in the register would be:
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*
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* CASL = 0b01
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* PTA = 0b01
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* CTP = 0b10
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* LDF = 0b01
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* RFTA = 0b011
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* RCD = 0b01
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*
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* If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
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* instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
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* defined as Trc rather than Trfc.
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* When using DIMM modules, most but not all of the required timing parameters can be read
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* from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
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* are not available from the EEPROM
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*/
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#include <common.h>
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#include "mip405.h"
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#include <asm/processor.h>
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#include <405gp_i2c.h>
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#include <miiphy.h>
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#include "../common/common_util.h"
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#include <i2c.h>
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extern block_dev_desc_t * scsi_get_dev(int dev);
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extern block_dev_desc_t * ide_get_dev(int dev);
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#undef SDRAM_DEBUG
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#define FALSE 0
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#define TRUE 1
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/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
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#ifndef __ldiv_t_defined
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typedef struct {
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long int quot; /* Quotient */
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long int rem; /* Remainder */
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} ldiv_t;
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extern ldiv_t ldiv (long int __numer, long int __denom);
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# define __ldiv_t_defined 1
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#endif
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#define PLD_PART_REG PER_PLD_ADDR + 0
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#define PLD_VERS_REG PER_PLD_ADDR + 1
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#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
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#define PLD_IRQ_REG PER_PLD_ADDR + 3
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#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
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#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
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#define MEGA_BYTE (1024*1024)
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typedef struct {
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unsigned char boardtype; /* Board revision and Population Options */
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unsigned char cal; /* cas Latency (will be programmend as cal-1) */
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unsigned char trp; /* datain27 in clocks */
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unsigned char trcd; /* datain29 in clocks */
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unsigned char tras; /* datain30 in clocks */
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unsigned char tctp; /* tras - trcd in clocks */
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unsigned char am; /* Address Mod (will be programmed as am-1) */
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unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
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unsigned char ecc; /* if true, ecc is enabled */
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} sdram_t;
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const sdram_t sdram_table[] = {
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{ 0x0f, /* Rev A, 128MByte -1 Board */
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3, /* Case Latenty = 3 */
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3, /* trp 20ns / 7.5 ns datain[27] */
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3, /* trcd 20ns /7.5 ns (datain[29]) */
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6, /* tras 44ns /7.5 ns (datain[30]) */
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4, /* tcpt 44 - 20ns = 24ns */
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3, /* Address Mode = 3 */
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5, /* size value */
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1}, /* ECC enabled */
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{ 0x07, /* Rev A, 64MByte -2 Board */
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3, /* Case Latenty = 3 */
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3, /* trp 20ns / 7.5 ns datain[27] */
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3, /* trcd 20ns /7.5 ns (datain[29]) */
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6, /* tras 44ns /7.5 ns (datain[30]) */
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4, /* tcpt 44 - 20ns = 24ns */
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2, /* Address Mode = 2 */
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4, /* size value */
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1}, /* ECC enabled */
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{ 0x03, /* Rev A, 128MByte -4 Board */
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3, /* Case Latenty = 3 */
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3, /* trp 20ns / 7.5 ns datain[27] */
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3, /* trcd 20ns /7.5 ns (datain[29]) */
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6, /* tras 44ns /7.5 ns (datain[30]) */
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4, /* tcpt 44 - 20ns = 24ns */
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3, /* Address Mode = 3 */
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5, /* size value */
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1}, /* ECC enabled */
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{ 0xff, /* terminator */
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0xff,
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0xff,
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0xff,
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0xff,
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0xff,
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0xff,
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0xff }
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};
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void SDRAM_err (const char *s)
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{
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#ifndef SDRAM_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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(void) get_clocks ();
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gd->baudrate = 9600;
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serial_init ();
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#endif
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serial_puts ("\n");
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serial_puts (s);
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serial_puts ("\n enable SDRAM_DEBUG for more info\n");
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for (;;);
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}
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unsigned char get_board_revcfg (void)
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{
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out8 (PER_BOARD_ADDR, 0);
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return (in8 (PER_BOARD_ADDR));
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}
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#ifdef SDRAM_DEBUG
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void write_hex (unsigned char i)
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{
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char cc;
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cc = i >> 4;
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cc &= 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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cc = i & 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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}
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void write_4hex (unsigned long val)
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{
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write_hex ((unsigned char) (val >> 24));
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write_hex ((unsigned char) (val >> 16));
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write_hex ((unsigned char) (val >> 8));
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write_hex ((unsigned char) val);
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}
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#endif
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int init_sdram (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long tmp, baseaddr;
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unsigned short i;
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unsigned char trp_clocks,
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trcd_clocks,
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tras_clocks,
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trc_clocks,
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tctp_clocks;
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unsigned char cal_val;
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unsigned char bc;
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unsigned long pbcr, sdram_tim, sdram_bank;
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unsigned long *p;
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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(void) get_clocks ();
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gd->baudrate = 9600;
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serial_init ();
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serial_puts ("\nInitializing SDRAM, Please stand by");
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mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
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pbcr = mfdcr (ebccfgd);
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if ((pbcr & 0x00002000) == 0) {
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/* MPS Boot, set up the flash */
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mtdcr (ebccfga, pb1ap);
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mtdcr (ebccfgd, FLASH_AP);
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mtdcr (ebccfga, pb1cr);
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mtdcr (ebccfgd, FLASH_CR);
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} else {
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/* Flash boot, set up the MPS */
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mtdcr (ebccfga, pb1ap);
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mtdcr (ebccfgd, MPS_AP);
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mtdcr (ebccfga, pb1cr);
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mtdcr (ebccfgd, MPS_CR);
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}
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/* set up UART0 (CS2) and UART1 (CS3) */
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mtdcr (ebccfga, pb2ap);
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mtdcr (ebccfgd, UART0_AP);
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mtdcr (ebccfga, pb2cr);
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mtdcr (ebccfgd, UART0_CR);
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mtdcr (ebccfga, pb3ap);
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mtdcr (ebccfgd, UART1_AP);
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mtdcr (ebccfga, pb3cr);
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mtdcr (ebccfgd, UART1_CR);
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/* set up the pld */
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mtdcr (ebccfga, pb7ap);
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mtdcr (ebccfgd, PLD_AP);
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mtdcr (ebccfga, pb7cr);
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mtdcr (ebccfgd, PLD_CR);
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/* set up the board rev reg */
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mtdcr (ebccfga, pb5ap);
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mtdcr (ebccfgd, BOARD_AP);
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mtdcr (ebccfga, pb5cr);
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mtdcr (ebccfgd, BOARD_CR);
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#ifdef SDRAM_DEBUG
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out8 (PER_BOARD_ADDR, 0);
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bc = in8 (PER_BOARD_ADDR);
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serial_puts ("\nBoard Rev: ");
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write_hex (bc);
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serial_puts (" (PLD=");
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bc = in8 (PLD_BOARD_CFG_REG);
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write_hex (bc);
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serial_puts (")\n");
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#endif
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bc = get_board_revcfg ();
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#ifdef SDRAM_DEBUG
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serial_puts ("\nstart SDRAM Setup\n");
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serial_puts ("\nBoard Rev: ");
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write_hex (bc);
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serial_puts ("\n");
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#endif
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i = 0;
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baseaddr = CFG_SDRAM_BASE;
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while (sdram_table[i].sz != 0xff) {
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if (sdram_table[i].boardtype == bc)
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break;
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i++;
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}
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if (sdram_table[i].boardtype != bc)
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SDRAM_err ("No SDRAM table found for this board!!!\n");
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#ifdef SDRAM_DEBUG
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serial_puts (" found table ");
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write_hex (i);
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serial_puts (" \n");
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#endif
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cal_val = sdram_table[i].cal - 1; /* Cas Latency */
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trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
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trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
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tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
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/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
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tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
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/* trc_clocks is sum of trp_clocks + tras_clocks */
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trc_clocks = trp_clocks + tras_clocks;
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/* get SDRAM timing register */
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mtdcr (memcfga, mem_sdtr1);
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sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
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/* insert CASL value */
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sdram_tim |= ((unsigned long) (cal_val)) << 23;
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/* insert PTA value */
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sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
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/* insert CTP value */
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sdram_tim |=
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((unsigned long) (trc_clocks - trp_clocks -
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trcd_clocks)) << 16;
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/* insert LDF (always 01) */
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sdram_tim |= ((unsigned long) 0x01) << 14;
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/* insert RFTA value */
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sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
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/* insert RCD value */
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sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
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tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
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/* insert SZ value; */
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tmp |= ((unsigned long) sdram_table[i].sz << 17);
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/* get SDRAM bank 0 register */
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mtdcr (memcfga, mem_mb0cf);
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sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
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sdram_bank |= (baseaddr | tmp | 0x01);
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#ifdef SDRAM_DEBUG
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serial_puts ("sdtr: ");
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write_4hex (sdram_tim);
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serial_puts ("\n");
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#endif
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/* write SDRAM timing register */
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mtdcr (memcfga, mem_sdtr1);
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mtdcr (memcfgd, sdram_tim);
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#ifdef SDRAM_DEBUG
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serial_puts ("mb0cf: ");
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write_4hex (sdram_bank);
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serial_puts ("\n");
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#endif
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/* write SDRAM bank 0 register */
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mtdcr (memcfga, mem_mb0cf);
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mtdcr (memcfgd, sdram_bank);
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if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
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/* get SDRAM refresh interval register */
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mtdcr (memcfga, mem_rtr);
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tmp = mfdcr (memcfgd) & ~0x3FF80000;
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tmp |= 0x07F00000;
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} else {
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/* get SDRAM refresh interval register */
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mtdcr (memcfga, mem_rtr);
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tmp = mfdcr (memcfgd) & ~0x3FF80000;
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tmp |= 0x05F00000;
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}
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/* write SDRAM refresh interval register */
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mtdcr (memcfga, mem_rtr);
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mtdcr (memcfgd, tmp);
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/* enable ECC if used */
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#if 1
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if (sdram_table[i].ecc) {
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/* disable checking for all banks */
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#ifdef SDRAM_DEBUG
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serial_puts ("disable ECC.. ");
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#endif
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mtdcr (memcfga, mem_ecccf);
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tmp = mfdcr (memcfgd);
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tmp &= 0xff0fffff; /* disable all banks */
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mtdcr (memcfga, mem_ecccf);
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/* set up SDRAM Controller with ECC enabled */
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#ifdef SDRAM_DEBUG
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serial_puts ("setup SDRAM Controller.. ");
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#endif
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mtdcr (memcfgd, tmp);
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mtdcr (memcfga, mem_mcopt1);
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tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
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mtdcr (memcfga, mem_mcopt1);
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mtdcr (memcfgd, tmp);
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udelay (600);
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#ifdef SDRAM_DEBUG
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serial_puts ("fill the memory..\n");
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#endif
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serial_puts (".");
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/* now, fill all the memory */
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tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
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p = (unsigned long) 0;
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while ((unsigned long) p < tmp) {
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*p++ = 0L;
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if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
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serial_puts (".");
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}
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/* enable bank 0 */
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serial_puts (".");
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#ifdef SDRAM_DEBUG
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serial_puts ("enable ECC\n");
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#endif
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udelay (400);
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mtdcr (memcfga, mem_ecccf);
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tmp = mfdcr (memcfgd);
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tmp |= 0x00800000; /* enable bank 0 */
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mtdcr (memcfgd, tmp);
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udelay (400);
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} else
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#endif
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{
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/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
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mtdcr (memcfga, mem_mcopt1);
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tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
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mtdcr (memcfga, mem_mcopt1);
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mtdcr (memcfgd, tmp);
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udelay (400);
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}
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serial_puts ("\n");
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return (0);
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}
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int board_pre_init (void)
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{
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init_sdram ();
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the PIP405 board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
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| IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
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| IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for MIP405 board:
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| An interrupt taken for the SouthBridge (IRQ 25) indicates that
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| the Interrupt Controller in the South Bridge has caused the
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| interrupt. The IC must be read to determine which device
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| caused the interrupt.
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+-------------------------------------------------------------------------*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
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mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr (uictr, 0x10000000); /* set int trigger levels */
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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/*
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* Get some PLD Registers
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*/
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unsigned short get_pld_parvers (void)
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{
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unsigned short result;
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unsigned char rc;
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rc = in8 (PLD_PART_REG);
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result = (unsigned short) rc << 8;
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rc = in8 (PLD_VERS_REG);
|
|
result |= rc;
|
|
return result;
|
|
}
|
|
|
|
|
|
|
|
void user_led0 (unsigned char on)
|
|
{
|
|
if (on)
|
|
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
|
|
else
|
|
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
|
|
}
|
|
|
|
|
|
void ide_set_reset (int idereset)
|
|
{
|
|
/* if reset = 1 IDE reset will be asserted */
|
|
if (idereset)
|
|
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
|
|
else {
|
|
udelay (10000);
|
|
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
|
|
}
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
/*
|
|
* Check Board Identity:
|
|
*/
|
|
|
|
int checkboard (void)
|
|
{
|
|
unsigned char s[50];
|
|
unsigned char bc, var, rc;
|
|
int i;
|
|
backup_t *b = (backup_t *) s;
|
|
|
|
puts ("Board: ");
|
|
|
|
bc = get_board_revcfg ();
|
|
var = ~bc;
|
|
var &= 0xf;
|
|
rc = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
rc <<= 1;
|
|
rc += (var & 0x1);
|
|
var >>= 1;
|
|
}
|
|
rc++;
|
|
i = getenv_r ("serial#", s, 32);
|
|
if ((i == 0) || strncmp (s, "MIP405", 6)) {
|
|
get_backup_values (b);
|
|
if (strncmp (b->signature, "MPL\0", 4) != 0) {
|
|
puts ("### No HW ID - assuming MIP405");
|
|
printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf));
|
|
} else {
|
|
b->serial_name[6] = 0;
|
|
printf ("%s-%d Rev %c SN: %s", b->serial_name, rc,
|
|
'A' + ((bc >> 4) & 0xf), &b->serial_name[7]);
|
|
}
|
|
} else {
|
|
s[6] = 0;
|
|
printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf),
|
|
&s[7]);
|
|
}
|
|
bc = in8 (PLD_EXT_CONF_REG);
|
|
printf (" Boot Config: 0x%x\n", bc);
|
|
return (0);
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
/* ------------------------------------------------------------------------- */
|
|
/*
|
|
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
|
|
the necessary info for SDRAM controller configuration
|
|
*/
|
|
/* ------------------------------------------------------------------------- */
|
|
/* ------------------------------------------------------------------------- */
|
|
static int test_dram (unsigned long ramsize);
|
|
|
|
long int initdram (int board_type)
|
|
{
|
|
|
|
unsigned long bank_reg[4], tmp, bank_size;
|
|
int i, ds;
|
|
unsigned long TotalSize;
|
|
|
|
ds = 0;
|
|
/* since the DRAM controller is allready set up, calculate the size with the
|
|
bank registers */
|
|
mtdcr (memcfga, mem_mb0cf);
|
|
bank_reg[0] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb1cf);
|
|
bank_reg[1] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb2cf);
|
|
bank_reg[2] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb3cf);
|
|
bank_reg[3] = mfdcr (memcfgd);
|
|
TotalSize = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
if ((bank_reg[i] & 0x1) == 0x1) {
|
|
tmp = (bank_reg[i] >> 17) & 0x7;
|
|
bank_size = 4 << tmp;
|
|
TotalSize += bank_size;
|
|
} else
|
|
ds = 1;
|
|
}
|
|
mtdcr (memcfga, mem_ecccf);
|
|
tmp = mfdcr (memcfgd);
|
|
|
|
if (!tmp)
|
|
printf ("No ");
|
|
printf ("ECC ");
|
|
|
|
test_dram (TotalSize * MEGA_BYTE);
|
|
return (TotalSize * MEGA_BYTE);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
extern int mem_test (unsigned long start, unsigned long ramsize,
|
|
int quiet);
|
|
|
|
static int test_dram (unsigned long ramsize)
|
|
{
|
|
#ifdef SDRAM_DEBUG
|
|
mem_test (0L, ramsize, 1);
|
|
#endif
|
|
/* not yet implemented */
|
|
return (1);
|
|
}
|
|
|
|
int misc_init_r (void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
|
|
void print_mip405_rev (void)
|
|
{
|
|
unsigned char part, vers, cfg, rev;
|
|
|
|
cfg = get_board_revcfg ();
|
|
vers = cfg;
|
|
vers &= 0xf;
|
|
rev = (((vers & 0x1) ? 0x8 : 0) |
|
|
((vers & 0x2) ? 0x4 : 0) |
|
|
((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));
|
|
|
|
part = in8 (PLD_PART_REG);
|
|
vers = in8 (PLD_VERS_REG);
|
|
printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n",
|
|
(16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);
|
|
}
|
|
|
|
|
|
int last_stage_init (void)
|
|
{
|
|
/* write correct LED configuration */
|
|
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
|
|
printf ("Error writing to the PHY\n");
|
|
}
|
|
/* since LED/CFG2 is not connected on the -2,
|
|
* write to correct capability information */
|
|
if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
|
|
printf ("Error writing to the PHY\n");
|
|
}
|
|
print_mip405_rev ();
|
|
show_stdio_dev ();
|
|
check_env ();
|
|
return 0;
|
|
}
|
|
|
|
/***************************************************************************
|
|
* some helping routines
|
|
*/
|
|
|
|
int overwrite_console (void)
|
|
{
|
|
return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
|
|
}
|
|
|
|
|
|
/************************************************************************
|
|
* Print MIP405 Info
|
|
************************************************************************/
|
|
void print_mip405_info (void)
|
|
{
|
|
unsigned char part, vers, cfg, irq_reg, com_mode, ext;
|
|
|
|
part = in8 (PLD_PART_REG);
|
|
vers = in8 (PLD_VERS_REG);
|
|
cfg = in8 (PLD_BOARD_CFG_REG);
|
|
irq_reg = in8 (PLD_IRQ_REG);
|
|
com_mode = in8 (PLD_COM_MODE_REG);
|
|
ext = in8 (PLD_EXT_CONF_REG);
|
|
|
|
printf ("PLD Part %d version %d\n", part, vers);
|
|
printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
|
|
printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
|
|
(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
|
|
printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
|
|
printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
|
|
printf ("Test ist %x\n", com_mode);
|
|
printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
|
|
(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
|
|
(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
|
|
(ext >> 6) & 0x1, (ext >> 7) & 0x1);
|
|
printf ("SER1 uses handshakes %s\n",
|
|
(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
|
|
printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
|
|
printf ("IRQs:\n");
|
|
printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
|
|
printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
|
|
printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
|
|
printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
|
|
printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
|
|
printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
|
|
}
|
|
|
|
|
|
|