upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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402 lines
15 KiB
402 lines
15 KiB
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
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/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
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/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
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/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
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/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
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/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
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/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
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/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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#if defined(CONFIG_SOFT_I2C)
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/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
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/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
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#else
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#if defined(CONFIG_HARD_I2C)
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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#else /* normal I/O port pins */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
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#endif
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#endif
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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/* ------------------------------------------------------------------------- */
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/* Check Board Identity:
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*/
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int checkboard (void)
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{
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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puts ("Board: ");
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if (!i || strncmp (str, "TQM82", 5)) {
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puts ("### No HW ID - assuming TQM8260\n");
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return (0);
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}
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puts (str);
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
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*
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* This routine performs standard 8260 initialization sequence
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* and calculates the available memory size. It may be called
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* several times to try different SDRAM configurations on both
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* 60x and local buses.
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*/
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static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
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ulong orx, volatile uchar * base)
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{
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volatile uchar c = 0xff;
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ulong cnt, val;
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volatile ulong *addr;
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volatile uint *sdmr_ptr;
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volatile uint *orx_ptr;
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int i;
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ulong save[32]; /* to make test non-destructive */
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ulong maxsize;
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/* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be
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* mapped by the controller. That means, that the initial mapping has
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* to be (at least) twice as large as the maximum expected size.
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*/
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maxsize = (1 + (~orx | 0x7fff)) / 2;
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/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
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* we are configuring CS1 if base != 0
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*/
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sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
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orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
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*orx_ptr = orx;
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
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*
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* "At system reset, initialization software must set up the
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* programmable parameters in the memory controller banks registers
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
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* system software should execute the following initialization sequence
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* for each SDRAM device.
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*
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* 1. Issue a PRECHARGE-ALL-BANKS command
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* 2. Issue eight CBR REFRESH commands
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* 3. Issue a MODE-SET command to initialize the mode register
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*
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
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*/
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*sdmr_ptr = sdmr | PSDMR_OP_PREA;
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_MRW;
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*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
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*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
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*base = c;
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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i = 0;
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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addr = (volatile ulong *) base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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addr = (volatile ulong *) base;
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save[i] = *addr;
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*addr = 0;
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = (volatile ulong *) base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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/* Write the actual size to ORx
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*/
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*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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#ifndef CFG_RAMBOOT
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long size8, size9;
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#endif
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long psize, lsize;
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psize = 16 * 1024 * 1024;
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lsize = 0;
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memctl->memc_psrt = CFG_PSRT;
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memctl->memc_mptpr = CFG_MPTPR;
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#if 0 /* Just for debugging */
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#define prt_br_or(brX,orX) do { \
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ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
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ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
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printf ("\n" \
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#brX " 0x%08x " #orX " 0x%08x " \
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"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
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memctl->memc_ ## brX, memctl->memc_ ## orX, \
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start, start+sizem, (sizem+1)>>20); \
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} while (0)
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prt_br_or (br0, or0);
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prt_br_or (br1, or1);
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prt_br_or (br2, or2);
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prt_br_or (br3, or3);
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#endif
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#ifndef CFG_RAMBOOT
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/* 60x SDRAM setup:
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*/
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size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
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(uchar *) CFG_SDRAM_BASE);
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size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
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(uchar *) CFG_SDRAM_BASE);
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if (size8 < size9) {
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psize = size9;
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printf ("(60x:9COL - %ld MB, ", psize >> 20);
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} else {
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psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
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(uchar *) CFG_SDRAM_BASE);
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printf ("(60x:8COL - %ld MB, ", psize >> 20);
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}
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/* Local SDRAM setup:
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*/
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#ifdef CFG_INIT_LOCAL_SDRAM
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memctl->memc_lsrt = CFG_LSRT;
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size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
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(uchar *) SDRAM_BASE2_PRELIM);
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|
size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
|
|
(uchar *) SDRAM_BASE2_PRELIM);
|
|
|
|
if (size8 < size9) {
|
|
lsize = size9;
|
|
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
|
|
} else {
|
|
lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
|
|
(uchar *) SDRAM_BASE2_PRELIM);
|
|
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
|
|
}
|
|
|
|
#if 0
|
|
/* Set up BR2 so that the local SDRAM goes
|
|
* right after the 60x SDRAM
|
|
*/
|
|
memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
|
|
(CFG_SDRAM_BASE + psize);
|
|
#endif
|
|
#endif /* CFG_INIT_LOCAL_SDRAM */
|
|
#endif /* CFG_RAMBOOT */
|
|
|
|
icache_enable ();
|
|
|
|
return (psize);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|