upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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563 lines
15 KiB
563 lines
15 KiB
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include <i2c.h>
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#include <command.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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static void puma_status (void);
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static void puma_set_mode (int mode);
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static int puma_init_done (void);
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static void puma_load (ulong addr, ulong len);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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/*
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* 50 MHz SDRAM access using UPM A
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*/
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
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0x1ffddc47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPM RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
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0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7ffffc07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* PUMA access using UPM B
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*/
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const uint puma_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_,
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/*
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* Precharge and MRS
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7ffffc07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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*/
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int checkboard (void)
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{
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puts ("Board: Siemens PCU E\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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long int size_b0, reg;
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int i;
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/*
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* Configure UPMA for SDRAM
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*/
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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memctl->memc_mptpr = CFG_MPTPR;
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/* burst length=4, burst type=sequential, CAS latency=2 */
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 2 to the SDRAM bank at preliminary address.
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*/
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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memctl->memc_or5 = CFG_OR5_PRELIM;
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memctl->memc_br5 = CFG_BR5_PRELIM;
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#else /* XXX */
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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#endif /* XXX */
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/* initialize memory address register */
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memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
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/* mode initialization (offset 5) */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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udelay (200); /* 0x8000A105 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
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#else /* XXX */
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udelay (200); /* 0x80004105 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
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#endif /* XXX */
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/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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udelay (1); /* 0x8000A830 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
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#else /* XXX */
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udelay (1); /* 0x80004830 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
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#endif /* XXX */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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udelay (1); /* 0x8000A106 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
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#else /* XXX */
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udelay (1); /* 0x80004106 */
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memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
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#endif /* XXX */
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reg = memctl->memc_mamr;
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reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
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reg |= MAMR_TLFA_4X; /* ... to 4x */
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reg |= MAMR_PTAE; /* enable refresh */
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memctl->memc_mamr = reg;
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udelay (200);
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/* Need at least 10 DRAM accesses to stabilize */
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for (i = 0; i < 10; ++i) {
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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volatile unsigned long *addr =
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(volatile unsigned long *) SDRAM_BASE5_PRELIM;
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#else /* XXX */
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volatile unsigned long *addr =
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(volatile unsigned long *) SDRAM_BASE2_PRELIM;
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#endif /* XXX */
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unsigned long val;
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val = *(addr + i);
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*(addr + i) = val;
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}
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/*
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* Check Bank 0 Memory Size for re-configuration
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*/
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
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#else /* XXX */
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size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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#endif /* XXX */
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memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
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/*
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* Final mapping:
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*/
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
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memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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#else /* XXX */
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
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memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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#endif /* XXX */
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udelay (1000);
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/*
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* Configure UPMB for PUMA
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*/
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upmconfig (UPMB, (uint *) puma_table,
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sizeof (puma_table) / sizeof (uint));
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
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#else /* XXX */
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#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
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CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
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#endif /* XXX */
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#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
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void reset_phy (void)
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{
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immap_t *immr = (immap_t *) CFG_IMMR;
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ulong value;
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/* Configure all needed port pins for GPIO */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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# ifdef CFG_ETH_MDDIS_VALUE
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immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
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# else
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immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
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# endif
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immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
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immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
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immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
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#endif /* XXX */
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immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
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immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
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value = immr->im_cpm.cp_pbdat;
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/* Assert Powerdown and Reset signals */
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value |= CFG_PB_ETH_POWERDOWN;
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value &= ~(CFG_PB_ETH_RESET);
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/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
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#if !PCU_E_WITH_SWAPPED_CS
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# ifdef CFG_ETH_MDDIS_VALUE
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value |= CFG_PB_ETH_MDDIS;
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# else
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value &= ~(CFG_PB_ETH_MDDIS);
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# endif
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#endif
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#ifdef CFG_ETH_CFG1_VALUE
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value |= CFG_PB_ETH_CFG1;
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#else
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value &= ~(CFG_PB_ETH_CFG1);
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#endif
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#ifdef CFG_ETH_CFG2_VALUE
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value |= CFG_PB_ETH_CFG2;
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#else
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value &= ~(CFG_PB_ETH_CFG2);
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#endif
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#ifdef CFG_ETH_CFG3_VALUE
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value |= CFG_PB_ETH_CFG3;
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#else
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value &= ~(CFG_PB_ETH_CFG3);
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#endif
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/* Drive output signals to initial state */
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immr->im_cpm.cp_pbdat = value;
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immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
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udelay (10000);
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/* De-assert Ethernet Powerdown */
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immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
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udelay (10000);
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/* de-assert RESET signal of PHY */
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immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
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udelay (1000);
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}
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/*-----------------------------------------------------------------------
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* Board Special Commands: access functions for "PUMA" FPGA
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_BSP) || defined(CONFIG_CMD_BSP)
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#define PUMA_READ_MODE 0
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#define PUMA_LOAD_MODE 1
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int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr, len;
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switch (argc) {
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case 2: /* PUMA reset */
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if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
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puma_status ();
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return 0;
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}
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break;
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case 4: /* PUMA load addr len */
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if (strcmp (argv[1], "load") != 0)
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break;
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addr = simple_strtoul (argv[2], NULL, 16);
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len = simple_strtoul (argv[3], NULL, 16);
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printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
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addr, len, len);
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puma_load (addr, len);
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return 0;
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default:
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break;
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}
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD (puma, 4, 1, do_puma,
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"puma - access PUMA FPGA\n",
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"status - print PUMA status\n"
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"puma load addr len - load PUMA configuration data\n");
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#endif /* CFG_CMD_BSP */
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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static void puma_set_mode (int mode)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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/* disable PUMA in memory controller */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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memctl->memc_br3 = 0;
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#else /* XXX */
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memctl->memc_br4 = 0;
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#endif /* XXX */
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switch (mode) {
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case PUMA_READ_MODE:
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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memctl->memc_or3 = PUMA_CONF_OR_READ;
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memctl->memc_br3 = PUMA_CONF_BR_READ;
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#else /* XXX */
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memctl->memc_or4 = PUMA_CONF_OR_READ;
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memctl->memc_br4 = PUMA_CONF_BR_READ;
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#endif /* XXX */
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break;
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case PUMA_LOAD_MODE:
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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memctl->memc_or3 = PUMA_CONF_OR_LOAD;
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memctl->memc_br3 = PUMA_CONF_BR_LOAD;
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#else /* XXX */
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memctl->memc_or4 = PUMA_CONF_OR_READ;
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memctl->memc_br4 = PUMA_CONF_BR_READ;
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#endif /* XXX */
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break;
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}
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}
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
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static void puma_load (ulong addr, ulong len)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
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uchar *data = (uchar *) addr;
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int i;
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/* align length */
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if (len & 1)
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++len;
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/* Reset FPGA */
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immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
|
|
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
|
|
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
|
|
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
|
immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
|
|
immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
|
|
immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
|
|
immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
|
|
#else
|
|
immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
|
|
immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
|
|
immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
|
|
immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
|
|
#endif /* XXX */
|
|
udelay (100);
|
|
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
|
immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
|
|
#else
|
|
immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
|
|
#endif /* XXX */
|
|
|
|
/* wait until INIT indicates completion of reset */
|
|
for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
|
|
udelay (1000);
|
|
if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
|
|
break;
|
|
}
|
|
if (i == PUMA_INIT_TIMEOUT) {
|
|
printf ("*** PUMA init timeout ***\n");
|
|
return;
|
|
}
|
|
|
|
puma_set_mode (PUMA_LOAD_MODE);
|
|
|
|
while (len--)
|
|
*fpga_addr = *data++;
|
|
|
|
puma_set_mode (PUMA_READ_MODE);
|
|
|
|
puma_status ();
|
|
}
|
|
|
|
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
|
|
|
static void puma_status (void)
|
|
{
|
|
/* Check state */
|
|
printf ("PUMA initialization is %scomplete\n",
|
|
puma_init_done ()? "" : "NOT ");
|
|
}
|
|
|
|
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
|
|
|
static int puma_init_done (void)
|
|
{
|
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
|
|
|
/* make sure pin is GPIO input */
|
|
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
|
|
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
|
|
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
|
|
|
|
return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
int misc_init_r (void)
|
|
{
|
|
ulong addr = 0;
|
|
ulong len = 0;
|
|
char *s;
|
|
|
|
printf ("PUMA: ");
|
|
if (puma_init_done ()) {
|
|
printf ("initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
if ((s = getenv ("puma_addr")) != NULL)
|
|
addr = simple_strtoul (s, NULL, 16);
|
|
|
|
if ((s = getenv ("puma_len")) != NULL)
|
|
len = simple_strtoul (s, NULL, 16);
|
|
|
|
if ((!addr) || (!len)) {
|
|
printf ("net list undefined\n");
|
|
return 0;
|
|
}
|
|
|
|
printf ("loading... ");
|
|
|
|
puma_load (addr, len);
|
|
return (0);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|