upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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586 lines
19 KiB
586 lines
19 KiB
/*
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* (C) Copyright 2001
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* Stuart Hughes <stuarth@lineo.com>
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* This file is based on similar values for other boards found in other
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* U-Boot config files, and some that I found in the mpc8260ads manual.
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*
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* Note: my board is a PILOT rev.
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* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
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*/
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!! !!
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!! This configuration requires JP3 to be in position 1-2 to work !!
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!! To make it work for the default, the TEXT_BASE define in !!
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!! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
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!! 0xfff00000 !!
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!! The CFG_HRCW_MASTER define below must also be changed to match !!
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!! !!
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* allow serial and ethaddr to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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/*
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* Port pins used for bit-banged MII communictions (if applicable).
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*/
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#define MDIO_PORT 2 /* Port C */
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#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
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#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
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#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
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else iop->pdat &= ~0x00400000
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#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
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else iop->pdat &= ~0x00200000
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#define MIIDELAY udelay(1)
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers (see 28-13)
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* - Half duplex
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_INDEX */
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/* other options */
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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/* PCI */
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_BOOTDELAY 0
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#undef CONFIG_PCI_SCAN_SHOW
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x50
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#define CONFIG_BAUDRATE 115200
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/*
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* Command line configuration.
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*/
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#include <config_cmd_all.h>
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#undef CONFIG_CMD_BEDBUG
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#undef CONFIG_CMD_BMP
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#undef CONFIG_CMD_BSP
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#undef CONFIG_CMD_DATE
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#undef CONFIG_CMD_DHCP
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#undef CONFIG_CMD_DISPLAY
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#undef CONFIG_CMD_DOC
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#undef CONFIG_CMD_DTT
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#undef CONFIG_CMD_EEPROM
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#undef CONFIG_CMD_ELF
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#undef CONFIG_CMD_EXT2
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#undef CONFIG_CMD_FDC
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#undef CONFIG_CMD_FDOS
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#undef CONFIG_CMD_HWFLOW
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#undef CONFIG_CMD_IDE
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#undef CONFIG_CMD_JFFS2
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#undef CONFIG_CMD_KGDB
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#undef CONFIG_CMD_MMC
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#undef CONFIG_CMD_NAND
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#undef CONFIG_CMD_PCMCIA
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#undef CONFIG_CMD_REISER
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#undef CONFIG_CMD_SCSI
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#undef CONFIG_CMD_SPI
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#undef CONFIG_CMD_SNTP
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#undef CONFIG_CMD_VFD
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#undef CONFIG_CMD_UNIVERSE
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#undef CONFIG_CMD_USB
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#undef CONFIG_CMD_XIMG
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/* Define a command string that is automatically executed when no character
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* is read on the console interface withing "Boot Delay" after reset.
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*/
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#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
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#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
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#ifdef CONFIG_BOOT_ROOT_INITRD
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#define CONFIG_BOOTCOMMAND \
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"version;" \
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"echo;" \
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"bootp;" \
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"setenv bootargs root=/dev/ram0 rw " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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#endif /* CONFIG_BOOT_ROOT_INITRD */
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#ifdef CONFIG_BOOT_ROOT_NFS
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#define CONFIG_BOOTCOMMAND \
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"version;" \
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"echo;" \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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#endif /* CONFIG_BOOT_ROOT_NFS */
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/* Add support for a few extra bootp options like:
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* - File size
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* - DNS
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*/
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_BOOTFILESIZE | \
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CONFIG_BOOTP_DNS)
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#if defined(CONFIG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#endif
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
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/* for versions < 2.4.5-pre5 */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_FLASH_BASE 0xFE000000
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#define FLASH_BASE 0xFE000000
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
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#define CFG_FLASH_SIZE 8
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
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#undef CFG_FLASH_CHECKSUM
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/* this is stuff came out of the Motorola docs */
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/* Only change this if you also change the Hardware configuration Word */
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#define CFG_DEFAULT_IMMR 0x0F010000
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/* Set IMMR to 0xF0000000 or above to boot Linux */
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#define CFG_IMMR 0xF0000000
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#define CFG_BCSR 0xF8000000
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#define CFG_PCI_INT 0xF8200000 /* PCI interrupt controller */
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/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
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*/
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/*#define CONFIG_VERY_BIG_RAM 1*/
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)? This will normally auto-configure via the SPD.
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE 16
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#define SDRAM_SPD_ADDR 0x50
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/*-----------------------------------------------------------------------
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* BR2,BR3 - Base Register
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* Ref: Section 10.3.1 on page 10-14
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* OR2,OR3 - Option Register
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* Ref: Section 10.3.2 on page 10-16
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*-----------------------------------------------------------------------
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*/
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/* Bank 2,3 - SDRAM DIMM
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*/
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/* The BR2 is configured as follows:
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*
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* - Base address of 0x00000000
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* - 64 bit port size (60x bus only)
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* - Data errors checking is disabled
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* - Read and write access
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* - SDRAM 60x bus
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* - Access are handled by the memory controller according to MSEL
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* - Not used for atomic operations
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* - No data pipelining is done
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* - Valid
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*/
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#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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/* With a 64 MB DIMM, the OR2 is configured as follows:
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*
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* - 64 MB
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* - 4 internal banks per device
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* - Row start address bit is A8 with PSDMR[PBI] = 0
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* - 12 row address lines
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* - Back-to-back page mode
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* - Internal bank interleaving within save device enabled
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*/
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#if (CFG_SDRAM_SIZE == 64)
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#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A8 |\
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ORxS_NUMR_12)
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#elif (CFG_SDRAM_SIZE == 16)
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#define CFG_OR2_PRELIM (0xFF000C80)
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#else
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#error "INVALID SDRAM CONFIGURATION"
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#endif
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/*-----------------------------------------------------------------------
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* PSDMR - 60x Bus SDRAM Mode Register
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* Ref: Section 10.3.3 on page 10-21
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*-----------------------------------------------------------------------
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*/
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#if (CFG_SDRAM_SIZE == 64)
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/* With a 64 MB DIMM, the PSDMR is configured as follows:
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*
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* - Bank Based Interleaving,
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* - Refresh Enable,
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* - Address Multiplexing where A5 is output on A14 pin
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* (A6 on A15, and so on),
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* - use address pins A14-A16 as bank select,
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* - A9 is output on SDA10 during an ACTIVATE command,
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* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
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* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
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* is 3 clocks,
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* - earliest timing for READ/WRITE command after ACTIVATE command is
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* 2 clocks,
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* - earliest timing for PRECHARGE after last data was read is 1 clock,
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* - earliest timing for PRECHARGE after last data was written is 1 clock,
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* - CAS Latency is 2.
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*/
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#define CFG_PSDMR (PSDMR_RFEN |\
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PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_3W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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#elif (CFG_SDRAM_SIZE == 16)
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/* With a 16 MB DIMM, the PSDMR is configured as follows:
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*
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* configuration parameters found in Motorola documentation
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*/
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#define CFG_PSDMR (0x016EB452)
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#else
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#error "INVALID SDRAM CONFIGURATION"
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#endif
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#define RS232EN_1 0x02000002
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#define RS232EN_2 0x01000001
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#define FETHIEN 0x08000008
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#define FETH_RST 0x04000004
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
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/* 0x0EB2B645 */
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#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
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( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
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( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
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( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
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)
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/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
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/* #define CFG_HRCW_MASTER 0x0cb23645 */
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/* This value should actually be situated in the first 256 bytes of the FLASH
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which on the standard MPC8266ADS board is at address 0xFF800000
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The linker script places it at 0xFFF00000 instead.
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It still works, however, as long as the ADS board jumper JP3 is set to
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position 2-3 so the board is using the BCSR as Hardware Configuration Word
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If you want to use the one defined here instead, ust copy the first 256 bytes from
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0xfff00000 to 0xff800000 (for 8MB flash)
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- Rune
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*/
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#ifndef CFG_RAMBOOT
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# define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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# define CFG_ENV_SECT_SIZE 0x40000
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#else
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# define CFG_ENV_IS_IN_NVRAM 1
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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# define CFG_ENV_SIZE 0x200
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#endif /* CFG_RAMBOOT */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
|
* but Soft reset does not.
|
|
*
|
|
* HID1 has only read-only information - nothing to set.
|
|
*/
|
|
/*#define CFG_HID0_INIT 0 */
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#define CFG_HID0_INIT (HID0_ICE |\
|
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HID0_DCE |\
|
|
HID0_ICFI |\
|
|
HID0_DCI |\
|
|
HID0_IFEM |\
|
|
HID0_ABE)
|
|
|
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
|
|
|
|
#define CFG_HID2 0
|
|
|
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#define CFG_SYPCR 0xFFFFFFC3
|
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#define CFG_BCR 0x004C0000
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|
#define CFG_SIUMCR 0x4E64C000
|
|
#define CFG_SCCR 0x00000000
|
|
|
|
/* local bus memory map
|
|
*
|
|
* 0x00000000-0x03FFFFFF 64MB SDRAM
|
|
* 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
|
|
* 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
|
|
* 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
|
|
* 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
|
|
* 0xF8000000-0xF8007FFF 32KB BCSR
|
|
* 0xF8100000-0xF8107FFF 32KB ATM UNI
|
|
* 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
|
|
* 0xF8300000-0xF8307FFF 32KB EEPROM
|
|
* 0xFE000000-0xFFFFFFFF 32MB flash
|
|
*/
|
|
#define CFG_BR0_PRELIM 0xFE001801 /* flash */
|
|
#define CFG_OR0_PRELIM 0xFE000836
|
|
#define CFG_BR1_PRELIM (CFG_BCSR | 0x1801) /* BCSR */
|
|
#define CFG_OR1_PRELIM 0xFFFF8010
|
|
#define CFG_BR4_PRELIM 0xF8300801 /* EEPROM */
|
|
#define CFG_OR4_PRELIM 0xFFFF8846
|
|
#define CFG_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
|
|
#define CFG_OR5_PRELIM 0xFFFF8E36
|
|
#define CFG_BR8_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
|
|
#define CFG_OR8_PRELIM 0xFFFF8010
|
|
|
|
#define CFG_RMR 0x0001
|
|
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
|
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
|
#define CFG_RCCR 0
|
|
#define CFG_MPTPR 0x00001900
|
|
#define CFG_PSRT 0x00000021
|
|
|
|
/* This address must not exist */
|
|
#define CFG_RESET_ADDRESS 0xFCFFFF00
|
|
|
|
/* PCI Memory map (if different from default map */
|
|
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
|
|
#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
|
|
#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
|
|
PICMR_PREFETCH_EN)
|
|
|
|
/*
|
|
* These are the windows that allow the CPU to access PCI address space.
|
|
* All three PCI master windows, which allow the CPU to access PCI
|
|
* prefetch, non prefetch, and IO space (see below), must all fit within
|
|
* these windows.
|
|
*/
|
|
|
|
/* PCIBR0 */
|
|
#define CFG_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
|
|
#define CFG_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
|
|
/* PCIBR1 */
|
|
#define CFG_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
|
|
#define CFG_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
|
|
|
|
/*
|
|
* Master window that allows the CPU to access PCI Memory (prefetch).
|
|
* This window will be setup with the first set of Outbound ATU registers
|
|
* in the bridge.
|
|
*/
|
|
|
|
#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
|
|
#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
|
|
#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
|
|
#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
|
|
#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
|
|
|
|
/*
|
|
* Master window that allows the CPU to access PCI Memory (non-prefetch).
|
|
* This window will be setup with the second set of Outbound ATU registers
|
|
* in the bridge.
|
|
*/
|
|
|
|
#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
|
|
#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
|
|
#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
|
|
#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
|
|
#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
|
|
|
|
/*
|
|
* Master window that allows the CPU to access PCI IO space.
|
|
* This window will be setup with the third set of Outbound ATU registers
|
|
* in the bridge.
|
|
*/
|
|
|
|
#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
|
|
#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
|
|
#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
|
|
#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
|
|
#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
|
|
|
|
/*
|
|
* JFFS2 partitions
|
|
*
|
|
*/
|
|
/* No command line, one static partition, whole device */
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
#define CONFIG_JFFS2_DEV "nor0"
|
|
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
|
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
|
|
|
/* mtdparts command line support */
|
|
/*
|
|
#define CONFIG_JFFS2_CMDLINE
|
|
#define MTDIDS_DEFAULT ""
|
|
#define MTDPARTS_DEFAULT ""
|
|
*/
|
|
|
|
#endif /* __CONFIG_H */
|
|
|