upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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506 lines
15 KiB
506 lines
15 KiB
/*
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* Copyright 2004-2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mpc8568mds board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
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#define CONFIG_MPC8568 1 /* MPC8568 specific */
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#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
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#undef CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
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/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
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/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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* assume this is the AMD flash associated with the MDS board.
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* This allows booting from a promjet.
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*/
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#define CONFIG_ASSUME_AMD_FLASH
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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#endif /*Replace a call to get_clock_freq (after it is implemented)*/
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#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00400000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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/*
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* Make sure required options are set
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*/
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#ifndef CONFIG_SPD_EEPROM
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#error ("CONFIG_SPD_EEPROM is required")
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Local Bus Definitions
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*/
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/*
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* FLASH on the Local Bus
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* Two banks, 8M each, using the CFI driver.
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* Boot from BR0/OR0 bank at 0xff00_0000
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* Alternate BR1/OR1 bank at 0xff80_0000
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*
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* BR0, BR1:
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* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
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* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
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* Port Size = 16 bits = BRx[19:20] = 10
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* Use GPCM = BRx[24:26] = 000
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* Valid = BRx[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
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* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
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*
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* OR0, OR1:
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* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
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* Reserved ORx[17:18] = 11, confusion here?
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* CSNT = ORx[20] = 1
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* ACS = half cycle delay = ORx[21:22] = 11
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* SCY = 6 = ORx[24:27] = 0110
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* TRLX = use relaxed timing = ORx[29] = 1
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* EAD = use external address latch delay = OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
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*/
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#define CFG_BCSR_BASE 0xf8000000
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#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
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/*Chip select 0 - Flash*/
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#define CFG_BR0_PRELIM 0xfe001001
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#define CFG_OR0_PRELIM 0xfe006ff7
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/*Chip slelect 1 - BCSR*/
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#define CFG_BR1_PRELIM 0xf8000801
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#define CFG_OR1_PRELIM 0xffffe9f7
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/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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/*
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* SDRAM on the LocalBus
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*/
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#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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/*Chip select 2 - SDRAM*/
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#define CFG_BR2_PRELIM 0xf0001861
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#define CFG_OR2_PRELIM 0xfc006901
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#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
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#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
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/*
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* LSDMR masks
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*/
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#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
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#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
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#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
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#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
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#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
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#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
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#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
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#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
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#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
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#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
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#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
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#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
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/*
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* Common settings for all Local Bus SDRAM commands.
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* At run time, either BSMA1516 (for CPU 1.1)
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* or BSMA1617 (for CPU 1.0) (old)
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* is OR'ed in too.
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*/
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#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
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| CFG_LBC_LSDMR_PRETOACT7 \
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| CFG_LBC_LSDMR_ACTTORW7 \
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| CFG_LBC_LSDMR_BL8 \
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| CFG_LBC_LSDMR_WRC4 \
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| CFG_LBC_LSDMR_CL3 \
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| CFG_LBC_LSDMR_RFEN \
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)
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/*
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* The bcsr registers are connected to CS3 on MDS.
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* The new memory map places bcsr at 0xf8000000.
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*
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* For BR3, need:
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* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
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* port-size = 8-bits = BR[19:20] = 01
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* no parity checking = BR[21:22] = 00
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* GPMC for MSEL = BR[24:26] = 000
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
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*
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* For OR3, need:
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* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
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* disable buffer ctrl OR[19] = 0
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* CSNT OR[20] = 1
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* ACS OR[21:22] = 11
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* XACS OR[23] = 1
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* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
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* SETA OR[28] = 0
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* TRLX OR[29] = 1
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* EHTR OR[30] = 1
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* EAD extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
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*/
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#define CFG_BCSR (0xf8000000)
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/*Chip slelect 4 - PIB*/
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#define CFG_BR4_PRELIM 0xf8008801
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#define CFG_OR4_PRELIM 0xffffe9f7
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/*Chip select 5 - PIB*/
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#define CFG_BR5_PRELIM 0xf8010801
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#define CFG_OR5_PRELIM 0xffff69f7
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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/* Use the HUSH parser*/
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_FLAT_TREE 1
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#define CONFIG_OF_BOARD_SETUP 1
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/* maximum size of the flat tree (8K) */
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#define OF_FLAT_TREE_MAX_SIZE 8192
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#define OF_CPU "PowerPC,8568@0"
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#define OF_SOC "soc8568@e0000000"
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#define OF_TBCLK (bd->bi_busfreq / 8)
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#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/*
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* General PCI
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* Memory Addresses are mapped 1-1. I/O is mapped from 0
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
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#define CFG_PEX_MEM_BASE 0xa0000000
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#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
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#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PEX_IO_BASE 0x00000000
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#define CFG_PEX_IO_PHYS 0xe2800000
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#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
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#define CFG_SRIO_MEM_BASE 0xc0000000
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#undef CONFIG_TSEC3
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#undef CONFIG_TSEC4
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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/* Options are: eTSEC[0-3] */
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#define CONFIG_ETHPRIME "eTSEC0"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/* Cache Configuration */
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#define CFG_DCACHE_SIZE 32768
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#define CFG_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
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#endif
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#define CONFIG_IPADDR 192.168.1.253
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH /nfsroot
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#define CONFIG_BOOTFILE your.uImage
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=600000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=your.fdt.dtb\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs\0" \
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"ramargs=setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs\0" \
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#define CONFIG_NFSBOOTCOMMAND \
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"run nfsargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"run ramargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr $ramdiskaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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