upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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564 lines
16 KiB
564 lines
16 KiB
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* TQM8349 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define DEBUG
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#undef DEBUG
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC834X 1 /* MPC834X specific */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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#define CONFIG_TQM834X 1 /* TQM834X board specific */
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/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
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#define CFG_IMMR 0xff400000
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/* System clock. Primary input clock when in PCI host mode */
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#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
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/*
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* Local Bus LCRR
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* LCRR: DLL bypass, Clock divider is 8
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*
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* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
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*
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
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/* board pre init: do not call, nothing to do */
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#undef CONFIG_BOARD_EARLY_INIT_F
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/* detect the number of flash banks */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* DDR Setup
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*/
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00000000 /* memtest region */
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#define CFG_MEMTEST_END 0x00100000
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/*
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* FLASH on the Local Bus
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*/
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
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#define CFG_FLASH_SIZE 8 /* FLASH size in MB */
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/* buffered writes in the AMD chip set is not supported yet */
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#undef CFG_FLASH_USE_BUFFER_WRITE
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/*
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* FLASH bank number detection
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*/
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/*
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* When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
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* banks has to be determined at runtime and stored in a gloabl variable
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* tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
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* used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
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* should be made sufficiently large to accomodate the number of banks that
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* might actually be detected. Since most (all?) Flash related functions use
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* CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
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* defined as tqm834x_num_flash_banks.
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*/
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#define CFG_MAX_FLASH_BANKS_DETECT 2
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#ifndef __ASSEMBLY__
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extern int tqm834x_num_flash_banks;
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#endif
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#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
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#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
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/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
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BR_MS_GPCM | BR_PS_32 | BR_V)
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/* FLASH timing (0x0000_0c54) */
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#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
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OR_GPCM_SCY_5 | OR_GPCM_TRLX)
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#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
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/* disable remaining mappings */
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#define CFG_BR1_PRELIM 0x00000000
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#define CFG_OR1_PRELIM 0x00000000
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#define CFG_LBLAWBAR1_PRELIM 0x00000000
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#define CFG_LBLAWAR1_PRELIM 0x00000000
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#define CFG_BR2_PRELIM 0x00000000
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#define CFG_OR2_PRELIM 0x00000000
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#define CFG_LBLAWBAR2_PRELIM 0x00000000
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#define CFG_LBLAWAR2_PRELIM 0x00000000
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#define CFG_BR3_PRELIM 0x00000000
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#define CFG_OR3_PRELIM 0x00000000
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#define CFG_LBLAWBAR3_PRELIM 0x00000000
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#define CFG_LBLAWAR3_PRELIM 0x00000000
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#define CFG_BR4_PRELIM 0x00000000
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#define CFG_OR4_PRELIM 0x00000000
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#define CFG_LBLAWBAR4_PRELIM 0x00000000
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#define CFG_LBLAWAR4_PRELIM 0x00000000
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#define CFG_BR5_PRELIM 0x00000000
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#define CFG_OR5_PRELIM 0x00000000
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#define CFG_LBLAWBAR5_PRELIM 0x00000000
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#define CFG_LBLAWAR5_PRELIM 0x00000000
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#define CFG_BR6_PRELIM 0x00000000
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#define CFG_OR6_PRELIM 0x00000000
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#define CFG_LBLAWBAR6_PRELIM 0x00000000
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#define CFG_LBLAWAR6_PRELIM 0x00000000
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#define CFG_BR7_PRELIM 0x00000000
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#define CFG_OR7_PRELIM 0x00000000
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#define CFG_LBLAWBAR7_PRELIM 0x00000000
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#define CFG_LBLAWAR7_PRELIM 0x00000000
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/*
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* Monitor config
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*/
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
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#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
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#define CFG_I2C_SLAVE 0x7F /* slave address */
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#define CFG_I2C_OFFSET 0x3000
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/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
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#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
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/* I2C RTC */
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#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/* I2C SYSMON (LM75) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_LOW_TEMP -30
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#define CFG_DTT_HYSTERESIS 3
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/*
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_MII
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET)
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#define CFG_TSEC2_OFFSET 0x25000
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#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET)
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI
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#endif
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_PCI
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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/* PCI1 host bridge */
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#define CFG_PCI1_MEM_BASE 0xc0000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0xe2000000
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#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
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#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
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#undef CONFIG_EEPRO100
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#define CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
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#define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
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#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
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#endif
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#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#ifndef CFG_RAMBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#else
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#define CFG_NO_FLASH 1 /* Flash is not usable now */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CFG_RAMBOOT)
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#undef CONFIG_CMD_ENV
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#undef CONFIG_CMD_LOADS
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/*
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 32768
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#define CFG_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
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#endif
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#define CFG_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_CSB_TO_CLKIN_4X1 |\
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HRCWL_VCO_1X2 |\
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HRCWL_CORE_TO_CSB_2X1)
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#if defined(PCI_64BIT)
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_64_BIT_PCI |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCI2_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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#else
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_32_BIT_PCI |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_PCI2_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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#endif
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/* System IO Config */
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#define CFG_SICRH SICRH_TSOBI1
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#define CFG_SICRL SICRL_LDP_A
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/* i-cache and d-cache disabled */
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#define CFG_HID0_INIT 0x000000000
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#define CFG_HID0_FINAL CFG_HID0_INIT
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#define CFG_HID2 HID2_HBE
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/* DDR 0 - 512M */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in DCACHE @ 512M (no backing mem) */
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#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI */
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#ifdef CONFIG_PCI
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#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
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#else
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#define CFG_IBAT3L (0)
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#define CFG_IBAT3U (0)
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#define CFG_IBAT4L (0)
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#define CFG_IBAT4U (0)
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#define CFG_IBAT5L (0)
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#define CFG_IBAT5U (0)
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#endif
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|
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/* IMMRBAR */
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#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
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|
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/* FLASH */
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#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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|
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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#define CFG_DBAT3L CFG_IBAT3L
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#define CFG_DBAT3U CFG_IBAT3U
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#define CFG_DBAT4L CFG_IBAT4L
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#define CFG_DBAT4U CFG_IBAT4U
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#define CFG_DBAT5L CFG_IBAT5L
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#define CFG_DBAT5U CFG_IBAT5U
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#define CFG_DBAT6L CFG_IBAT6L
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#define CFG_DBAT6U CFG_IBAT6U
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
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|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
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|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
|
|
#endif
|
|
|
|
#define CONFIG_IPADDR 192.168.205.1
|
|
|
|
#define CONFIG_HOSTNAME tqm8349
|
|
#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
|
|
#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
|
|
|
|
#define CONFIG_SERVERIP 192.168.1.1
|
|
#define CONFIG_GATEWAYIP 192.168.1.1
|
|
#define CONFIG_NETMASK 255.255.255.0
|
|
|
|
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
|
|
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define CONFIG_PREBOOT "echo;" \
|
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
|
"echo"
|
|
|
|
#undef CONFIG_BOOTARGS
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"hostname=tqm83xx\0" \
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
":${hostname}:${netdev}:off panic=1\0" \
|
|
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
|
"flash_nfs=run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr}\0" \
|
|
"flash_self=run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
|
"bootm\0" \
|
|
"rootpath=/opt/eldk/ppc_6xx\0" \
|
|
"bootfile=/tftpboot/tqm83xx/uImage\0" \
|
|
"kernel_addr=80060000\0" \
|
|
"ramdisk_addr=80160000\0" \
|
|
"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
|
|
"update=protect off 80000000 8003ffff; " \
|
|
"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
|
|
"upd=run load;run update\0" \
|
|
""
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
|
|
/*
|
|
* JFFS2 partitions
|
|
*/
|
|
/* mtdparts command line support */
|
|
#define CONFIG_JFFS2_CMDLINE
|
|
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
|
|
|
|
/* default mtd partition table */
|
|
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
|
|
"1m(kernel),2m(initrd),"\
|
|
"-(user);"\
|
|
|
|
#endif /* __CONFIG_H */
|
|
|