upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
2.2 KiB
49 lines
2.2 KiB
/*
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* (C) Copyright 2008
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
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* Memory: DRAM (MCLK=40.000 MHz)
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*/
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static S1D_REGS regs_13505_640_480_16bpp[] =
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{
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{0x1B,0x00}, /* Miscellaneous Register */
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{0x23,0x20}, /* Performance Enhancement Register 1 */
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{0x01,0x30}, /* Memory Configuration Register */
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{0x22,0x24}, /* Performance Enhancement Register 0 */
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{0x02,0x25}, /* Panel Type Register */
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{0x03,0x00}, /* MOD Rate Register */
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{0x04,0x4F}, /* Horizontal Display Width Register */
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{0x05,0x0c}, /* Horizontal Non-Display Period Register */
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{0x06,0x00}, /* HRTC/FPLINE Start Position Register */
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{0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
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{0x08,0xDF}, /* Vertical Display Height Register 0 */
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{0x09,0x01}, /* Vertical Display Height Register 1 */
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{0x0A,0x3E}, /* Vertical Non-Display Period Register */
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{0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
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{0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
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{0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
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{0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
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{0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
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{0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
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{0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
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{0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
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{0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
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{0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
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{0x16,0x80}, /* Memory Address Offset Register 0 */
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{0x17,0x02}, /* Memory Address Offset Register 1 */
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{0x18,0x00}, /* Pixel Panning Register */
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{0x19,0x01}, /* Clock Configuration Register */
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{0x1A,0x00}, /* Power Save Configuration Register */
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{0x1C,0x00}, /* MD Configuration Readback Register 0 */
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{0x1E,0x06}, /* General IO Pins Configuration Register 0 */
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{0x1F,0x00}, /* General IO Pins Configuration Register 1 */
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{0x20,0x00}, /* General IO Pins Control Register 0 */
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{0x21,0x00}, /* General IO Pins Control Register 1 */
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{0x23,0x20}, /* Performance Enhancement Register 1 */
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{0x0D,0x15}, /* Display Mode Register */
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};
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