upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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503 lines
12 KiB
503 lines
12 KiB
/*
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* SPI flash probing
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*
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* Copyright (C) 2008 Atmel Corporation
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* Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
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* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/io.h>
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#include "sf_internal.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Read commands array */
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static u8 spi_read_cmds_array[] = {
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CMD_READ_ARRAY_SLOW,
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CMD_READ_ARRAY_FAST,
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CMD_READ_DUAL_OUTPUT_FAST,
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CMD_READ_DUAL_IO_FAST,
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CMD_READ_QUAD_OUTPUT_FAST,
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CMD_READ_QUAD_IO_FAST,
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};
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#ifdef CONFIG_SPI_FLASH_MACRONIX
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static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
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{
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u8 qeb_status;
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int ret;
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ret = spi_flash_cmd_read_status(flash, &qeb_status);
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if (ret < 0)
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return ret;
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if (qeb_status & STATUS_QEB_MXIC) {
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debug("SF: mxic: QEB is already set\n");
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} else {
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ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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#endif
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#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
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static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
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{
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u8 qeb_status;
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int ret;
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ret = spi_flash_cmd_read_config(flash, &qeb_status);
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if (ret < 0)
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return ret;
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if (qeb_status & STATUS_QEB_WINSPAN) {
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debug("SF: winspan: QEB is already set\n");
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} else {
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ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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#endif
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static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
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{
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switch (idcode0) {
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#ifdef CONFIG_SPI_FLASH_MACRONIX
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case SPI_FLASH_CFI_MFR_MACRONIX:
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return spi_flash_set_qeb_mxic(flash);
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#endif
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#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
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case SPI_FLASH_CFI_MFR_SPANSION:
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case SPI_FLASH_CFI_MFR_WINBOND:
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return spi_flash_set_qeb_winspan(flash);
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#endif
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#ifdef CONFIG_SPI_FLASH_STMICRO
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case SPI_FLASH_CFI_MFR_STMICRO:
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debug("SF: QEB is volatile for %02x flash\n", idcode0);
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return 0;
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#endif
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default:
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printf("SF: Need set QEB func for %02x flash\n", idcode0);
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return -1;
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}
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}
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static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
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struct spi_flash *flash)
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{
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const struct spi_flash_params *params;
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u8 cmd;
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u16 jedec = idcode[1] << 8 | idcode[2];
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u16 ext_jedec = idcode[3] << 8 | idcode[4];
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/* Validate params from spi_flash_params table */
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params = spi_flash_params_table;
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for (; params->name != NULL; params++) {
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if ((params->jedec >> 16) == idcode[0]) {
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if ((params->jedec & 0xFFFF) == jedec) {
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if (params->ext_jedec == 0)
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break;
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else if (params->ext_jedec == ext_jedec)
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break;
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}
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}
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}
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if (!params->name) {
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printf("SF: Unsupported flash IDs: ");
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printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
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idcode[0], jedec, ext_jedec);
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return -EPROTONOSUPPORT;
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}
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/* Assign spi data */
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flash->spi = spi;
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flash->name = params->name;
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flash->memory_map = spi->memory_map;
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flash->dual_flash = flash->spi->option;
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#ifdef CONFIG_DM_SPI_FLASH
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flash->flags = params->flags;
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#endif
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/* Assign spi_flash ops */
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#ifndef CONFIG_DM_SPI_FLASH
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flash->write = spi_flash_cmd_write_ops;
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#if defined(CONFIG_SPI_FLASH_SST)
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if (params->flags & SST_WR) {
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if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
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flash->write = sst_write_bp;
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else
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flash->write = sst_write_wp;
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}
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#endif
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flash->erase = spi_flash_cmd_erase_ops;
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flash->read = spi_flash_cmd_read_ops;
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#endif
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/* Compute the flash size */
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flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
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/*
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* The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
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* 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
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* the 0x4d00 Extended JEDEC code have 512b pages. All of the others
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* have 256b pages.
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*/
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if (ext_jedec == 0x4d00) {
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if ((jedec == 0x0215) || (jedec == 0x216))
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flash->page_size = 256;
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else
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flash->page_size = 512;
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} else {
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flash->page_size = 256;
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}
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flash->page_size <<= flash->shift;
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flash->sector_size = params->sector_size << flash->shift;
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flash->size = flash->sector_size * params->nr_sectors << flash->shift;
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#ifdef CONFIG_SF_DUAL_FLASH
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if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
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flash->size <<= 1;
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#endif
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/* Compute erase sector and command */
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if (params->flags & SECT_4K) {
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flash->erase_cmd = CMD_ERASE_4K;
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flash->erase_size = 4096 << flash->shift;
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} else if (params->flags & SECT_32K) {
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flash->erase_cmd = CMD_ERASE_32K;
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flash->erase_size = 32768 << flash->shift;
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} else {
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flash->erase_cmd = CMD_ERASE_64K;
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flash->erase_size = flash->sector_size;
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}
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/* Now erase size becomes valid sector size */
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flash->sector_size = flash->erase_size;
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/* Look for the fastest read cmd */
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cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
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if (cmd) {
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cmd = spi_read_cmds_array[cmd - 1];
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flash->read_cmd = cmd;
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} else {
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/* Go for default supported read cmd */
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flash->read_cmd = CMD_READ_ARRAY_FAST;
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}
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/* Not require to look for fastest only two write cmds yet */
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if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
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flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
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else
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/* Go for default supported write cmd */
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flash->write_cmd = CMD_PAGE_PROGRAM;
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/* Read dummy_byte: dummy byte is determined based on the
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* dummy cycles of a particular command.
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* Fast commands - dummy_byte = dummy_cycles/8
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* I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
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* For I/O commands except cmd[0] everything goes on no.of lines
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* based on particular command but incase of fast commands except
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* data all go on single line irrespective of command.
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*/
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switch (flash->read_cmd) {
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case CMD_READ_QUAD_IO_FAST:
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flash->dummy_byte = 2;
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break;
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case CMD_READ_ARRAY_SLOW:
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flash->dummy_byte = 0;
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break;
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default:
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flash->dummy_byte = 1;
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}
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/* Poll cmd selection */
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flash->poll_cmd = CMD_READ_STATUS;
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#ifdef CONFIG_SPI_FLASH_STMICRO
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if (params->flags & E_FSR)
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flash->poll_cmd = CMD_FLAG_STATUS;
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#endif
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/* Configure the BAR - discover bank cmds and read current bank */
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 curr_bank = 0;
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if (flash->size > SPI_FLASH_16MB_BOUN) {
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int ret;
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flash->bank_read_cmd = (idcode[0] == 0x01) ?
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CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
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flash->bank_write_cmd = (idcode[0] == 0x01) ?
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CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
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ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
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&curr_bank, 1);
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if (ret) {
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debug("SF: fail to read bank addr register\n");
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return ret;
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}
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flash->bank_curr = curr_bank;
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} else {
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flash->bank_curr = curr_bank;
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}
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#endif
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/* Flash powers up read-only, so clear BP# bits */
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#if defined(CONFIG_SPI_FLASH_ATMEL) || \
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defined(CONFIG_SPI_FLASH_MACRONIX) || \
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defined(CONFIG_SPI_FLASH_SST)
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spi_flash_cmd_write_status(flash, 0);
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#endif
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return 0;
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}
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#ifdef CONFIG_OF_CONTROL
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int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
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{
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fdt_addr_t addr;
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fdt_size_t size;
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int node;
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/* If there is no node, do nothing */
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node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
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if (node < 0)
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return 0;
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addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
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if (addr == FDT_ADDR_T_NONE) {
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debug("%s: Cannot decode address\n", __func__);
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return 0;
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}
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if (flash->size != size) {
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debug("%s: Memory map must cover entire device\n", __func__);
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return -1;
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}
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flash->memory_map = map_sysmem(addr, size);
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return 0;
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}
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#endif /* CONFIG_OF_CONTROL */
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/**
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* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
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*
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* @spi: Bus to probe
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* @flashp: Pointer to place to put flash info, which may be NULL if the
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* space should be allocated
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*/
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int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
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{
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u8 idcode[5];
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int ret;
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/* Setup spi_slave */
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if (!spi) {
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printf("SF: Failed to set up slave\n");
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return -ENODEV;
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}
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/* Claim spi bus */
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ret = spi_claim_bus(spi);
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if (ret) {
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debug("SF: Failed to claim SPI bus: %d\n", ret);
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return ret;
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}
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/* Read the ID codes */
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ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
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if (ret) {
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printf("SF: Failed to get idcodes\n");
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goto err_read_id;
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}
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#ifdef DEBUG
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printf("SF: Got idcodes\n");
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print_buffer(0, idcode, 1, sizeof(idcode), 0);
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#endif
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if (spi_flash_validate_params(spi, idcode, flash)) {
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ret = -EINVAL;
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goto err_read_id;
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}
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/* Set the quad enable bit - only for quad commands */
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if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
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(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
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(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
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if (spi_flash_set_qeb(flash, idcode[0])) {
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debug("SF: Fail to set QEB for %02x\n", idcode[0]);
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ret = -EINVAL;
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goto err_read_id;
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}
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}
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#ifdef CONFIG_OF_CONTROL
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if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
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debug("SF: FDT decode error\n");
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ret = -EINVAL;
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goto err_read_id;
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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printf("SF: Detected %s with page size ", flash->name);
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print_size(flash->page_size, ", erase size ");
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print_size(flash->erase_size, ", total ");
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print_size(flash->size, "");
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if (flash->memory_map)
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printf(", mapped at %p", flash->memory_map);
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puts("\n");
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#endif
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#ifndef CONFIG_SPI_FLASH_BAR
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if (((flash->dual_flash == SF_SINGLE_FLASH) &&
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(flash->size > SPI_FLASH_16MB_BOUN)) ||
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((flash->dual_flash > SF_SINGLE_FLASH) &&
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(flash->size > SPI_FLASH_16MB_BOUN << 1))) {
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puts("SF: Warning - Only lower 16MiB accessible,");
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puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
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}
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#endif
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/* Release spi bus */
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spi_release_bus(spi);
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return 0;
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err_read_id:
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spi_release_bus(spi);
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return ret;
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}
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#ifndef CONFIG_DM_SPI_FLASH
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struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
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{
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struct spi_flash *flash;
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/* Allocate space if needed (not used by sf-uclass */
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flash = calloc(1, sizeof(*flash));
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if (!flash) {
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debug("SF: Failed to allocate spi_flash\n");
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return NULL;
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}
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if (spi_flash_probe_slave(bus, flash)) {
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spi_free_slave(bus);
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free(flash);
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return NULL;
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}
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return flash;
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}
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struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
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unsigned int max_hz, unsigned int spi_mode)
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{
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struct spi_slave *bus;
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bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
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if (!bus)
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return NULL;
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return spi_flash_probe_tail(bus);
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}
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#ifdef CONFIG_OF_SPI_FLASH
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struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
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int spi_node)
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{
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struct spi_slave *bus;
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bus = spi_setup_slave_fdt(blob, slave_node, spi_node);
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if (!bus)
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return NULL;
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return spi_flash_probe_tail(bus);
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}
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#endif
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void spi_flash_free(struct spi_flash *flash)
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{
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spi_free_slave(flash->spi);
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free(flash);
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}
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#else /* defined CONFIG_DM_SPI_FLASH */
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static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len,
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void *buf)
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{
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struct spi_flash *flash = dev_get_uclass_priv(dev);
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return spi_flash_cmd_read_ops(flash, offset, len, buf);
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}
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int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
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const void *buf)
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{
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struct spi_flash *flash = dev_get_uclass_priv(dev);
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#if defined(CONFIG_SPI_FLASH_SST)
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if (flash->flags & SST_WR) {
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if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
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return sst_write_bp(flash, offset, len, buf);
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else
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return sst_write_wp(flash, offset, len, buf);
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}
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#endif
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return spi_flash_cmd_write_ops(flash, offset, len, buf);
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}
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int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
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{
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struct spi_flash *flash = dev_get_uclass_priv(dev);
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return spi_flash_cmd_erase_ops(flash, offset, len);
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}
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int spi_flash_std_probe(struct udevice *dev)
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{
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struct spi_slave *slave = dev_get_parentdata(dev);
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struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
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struct spi_flash *flash;
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flash = dev_get_uclass_priv(dev);
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flash->dev = dev;
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debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs);
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return spi_flash_probe_slave(slave, flash);
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}
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static const struct dm_spi_flash_ops spi_flash_std_ops = {
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.read = spi_flash_std_read,
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.write = spi_flash_std_write,
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.erase = spi_flash_std_erase,
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};
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static const struct udevice_id spi_flash_std_ids[] = {
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{ .compatible = "spi-flash" },
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{ }
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};
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U_BOOT_DRIVER(spi_flash_std) = {
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.name = "spi_flash_std",
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.id = UCLASS_SPI_FLASH,
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.of_match = spi_flash_std_ids,
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.probe = spi_flash_std_probe,
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.priv_auto_alloc_size = sizeof(struct spi_flash),
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.ops = &spi_flash_std_ops,
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};
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#endif /* CONFIG_DM_SPI_FLASH */
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