upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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112 lines
2.3 KiB
112 lines
2.3 KiB
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/sysreg.h>
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#include <asm/arch/hardware.h>
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#define HANDLER_MASK 0x00ffffff
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#define INTLEV_SHIFT 30
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#define INTLEV_MASK 0x00000003
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DECLARE_GLOBAL_DATA_PTR;
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/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
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volatile unsigned long timer_overflow;
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/*
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* Instead of dividing by get_tbclk(), multiply by this constant and
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* right-shift the result by 32 bits.
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*/
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static unsigned long tb_factor;
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unsigned long get_tbclk(void)
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{
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return gd->arch.cpu_hz;
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}
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unsigned long long get_ticks(void)
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{
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unsigned long lo, hi_now, hi_prev;
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do {
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hi_prev = timer_overflow;
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lo = sysreg_read(COUNT);
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hi_now = timer_overflow;
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} while (hi_prev != hi_now);
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return ((unsigned long long)hi_now << 32) | lo;
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}
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unsigned long get_timer(unsigned long base)
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{
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u64 now = get_ticks();
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now *= tb_factor;
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return (unsigned long)(now >> 32) - base;
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}
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/*
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* For short delays only. It will overflow after a few seconds.
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*/
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void __udelay(unsigned long usec)
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{
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unsigned long cycles;
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unsigned long base;
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unsigned long now;
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base = sysreg_read(COUNT);
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cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
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do {
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now = sysreg_read(COUNT);
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} while ((now - base) < cycles);
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}
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static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
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unsigned int priority)
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{
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extern void _evba(void);
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unsigned long intpr;
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unsigned long handler_addr = (unsigned long)handler;
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handler_addr -= (unsigned long)&_evba;
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if ((handler_addr & HANDLER_MASK) != handler_addr
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|| (priority & INTLEV_MASK) != priority)
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return -EINVAL;
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intpr = (handler_addr & HANDLER_MASK);
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intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
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writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr);
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return 0;
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}
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int timer_init(void)
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{
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extern void timer_interrupt_handler(void);
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u64 tmp;
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sysreg_write(COUNT, 0);
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tmp = (u64)CONFIG_SYS_HZ << 32;
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tmp += gd->arch.cpu_hz / 2;
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do_div(tmp, gd->arch.cpu_hz);
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tb_factor = (u32)tmp;
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if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
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return -EINVAL;
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/* For all practical purposes, this gives us an overflow interrupt */
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sysreg_write(COMPARE, 0xffffffff);
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return 0;
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}
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