upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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55 lines
1.3 KiB
55 lines
1.3 KiB
/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Sunxi platform dram register definition.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_H
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#define _SUNXI_DRAM_H
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#include <asm/io.h>
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#include <linux/types.h>
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/* dram regs definition */
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#if defined(CONFIG_MACH_SUN6I)
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#include <asm/arch/dram_sun6i.h>
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#elif defined(CONFIG_MACH_SUN8I)
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#include <asm/arch/dram_sun8i.h>
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#else
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#include <asm/arch/dram_sun4i.h>
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#endif
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unsigned long sunxi_dram_init(void);
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/*
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* Wait up to 1s for value to be set in given part of reg.
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*/
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static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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/*
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* Test if memory at offset offset matches memory at begin of DRAM
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*/
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static inline bool mctl_mem_matches(u32 offset)
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{
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/* Try to write different values to RAM at two addresses */
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
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/* Check if the same value is actually observed when reading back */
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return readl(CONFIG_SYS_SDRAM_BASE) ==
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readl(CONFIG_SYS_SDRAM_BASE + offset);
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}
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#endif /* _SUNXI_DRAM_H */
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